III-V compound semiconductor transistors—from planar to nanowire structures

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS application

Epitaxy from a Periodic Y–O Monolayer: Growth of Single-Crystal Hexagonal YAlO3 Perovskite

The role of an atomic-layer thick periodic Y–O array in inducing the epitaxial growth of single-crystal hexagonal YAlO3 perovskite (H-YAP) films was studied using high-angle annular dark-field and annular bright-field scanning transmission electron microscopy in conjunction with a spherical aberration-corrected probe and in situ reflection high-energy electron diffraction. We observed the Y–O array at the interface of amorphous atomic layer deposition (ALD) sub-nano-laminated (snl) Al2O3/Y2O3 multilayers and GaAs(111)A, with the first film deposition being three cycles of ALD-Y2O3. This thin array was a seed layer for growing the H-YAP from the ALD snl multilayers with 900 °C rapid thermal annealing (RTA). The annealed film only contained H-YAP with an excellent crystallinity and an atomically sharp interface with the substrate. The initial Y–O array became the bottom layer of H-YAP, bonding with Ga, the top layer of GaAs. Using a similar ALD snl multilayer, but with the first film deposition of three ALD-Al2O3 cycles, there was no observation of a periodic atomic array at the interface. RTA of the sample to 900 °C resulted in a non-uniform film, mixing amorphous regions and island-like H-YAP domains. The results indicate that the epitaxial H-YAP was induced from the atomic-layer thick periodic Y–O array, rather than from GaAs(111)A

III-V metal-oxide-semiconductor field-effect transistors with high kappa dielectrics

[[abstract]]Research efforts on achieving low interfacial density of states (D-it) as well as low electrical leakage currents on GaAs-based III-V compound semiconductors are reviewed. Emphasis is placed on ultra high vacuum (UHV) deposited Ga2O3(Gd2O3) and atomic layer deposition (ALD)-Al2O3 on GaAs and InGaAs. Ga2O3(Gd2O3), the novel oxide, which was electron-beam evaporated from a gallium-gadolinium-garnet target, has, for the first time, unpinned the Fermi level of the oxide/GaAs heterostructures. Interfacial chemical properties and band parameters of valence band offsets and conduction band offsets in the oxides/III-V heterostructures are studied and determined using X-ray photoelectron spectroscopy and electrical leakage transport measurements. The mechanism of III-V surface passivation is discussed. The mechanism of Fermi-level unpinning in ALD-Al2O3 ex-situ deposited on InGaAs were studied and unveiled. Systematic heat treatments under various gases and temperatures were studied to achieve low leakage currents of 10(-8)-10(-9) A/cm(2) and low D-it's in the range of (4-9) x 10(10)cm(-2)eV(-1) for Ga2O3(Gd2O3) on IDGaAS. By removing moisture from the oxide, thermodynamic stability of the Ga2O3(Gd2O3)/GaAs heterostructures was achieved with high temperature annealing, which is needed for fabricating inversion-channel metal-oxide-semiconductor filed-effect transistors (MOSFET's). The oxide remains amorphous and the interface remains intact with atomic smoothness and sharpness. Device performances of inversion-channel and depletion-mode Ill-V MOSFET's are reviewed, again with emphasis on the devices using Ga2O3(Gd2O3) as the gate dielectric.[[fileno]]2010113010121[[department]]物理

III-V compound semiconductor transistors-from planar to nanowire structures

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs-from planar to nanowire devices-integrated on a silicon platform to make these technologies suitable for future CMOS applications

Microscopic Views of Atomic and Molecular Oxygen Bonding with <i>epi</i> Ge(001)-2 × 1 Studied by High-Resolution Synchrotron Radiation Photoemission

In this paper, we investigate the embryonic stage of oxidation of an epi Ge(001)-2 &#215; 1 by atomic oxygen and molecular O2 via synchrotron radiation photoemission. The topmost buckled surface with the up- and down-dimer atoms, and the first subsurface layer behaves distinctly from the bulk by exhibiting surface core-level shifts in the Ge 3d core-level spectrum. The O2 molecules become dissociated upon reaching the epi Ge(001)-2 &#215; 1 surface. One of the O atoms removes the up-dimer atom and the other bonds with the underneath Ge atom in the subsurface layer. Atomic oxygen preferentially adsorbed on the epi Ge(001)-2 &#215;1 in between the up-dimer atoms and the underneath subsurface atoms, without affecting the down-dimer atoms. The electronic environment of the O-affiliated Ge up-dimer atoms becomes similar to that of the down-dimer atoms. They both exhibit an enrichment in charge, where the subsurface of the Ge layer is maintained in a charge-deficient state. The dipole moment that was originally generated in the buckled reconstruction no longer exists, thereby resulting in a decrease in the ionization potential. The down-dimer Ge atoms and the back-bonded subsurface atoms remain inert to atomic O and molecular O2, which might account for the low reliability in the Ge-related metal-oxide-semiconductor (MOS) devices