Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

1 Abstract NISC Modeling and Compilation

Running an application on a general purpose processor is not very efficient and implementing the whole application in hardware is not always possible. The best option is to run the application on a customized datapath that is designed based on the characteristics of the application. The instruction set interface in normal processors limits the possible customization of the datapath. In NISC, the instruction interface is removed and the datapath is directly controlled. Therefore, any customization in the datapath can be easily utilized by the supporting tools such as compiler and simulator and one set of such tools is enough to handle all kinds of datapaths. To achieve this goal, a generic model is needed to capture the datapath information that these tools require. In this report we present one such model and show how it can be used for simulation and compilation. We also explain the structure of a NISC compiler and show some preliminary experiments on multiple NISC architecture and their comparison with MIPS architecture

Hybrid Compiled Simulation: An Efficient Technique for Instruction- Set Architecture Simulation 1

Instruction-set simulators are critical tools for the exploration and validation of new processor architectures. Due to the increasing complexity of architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility and compilation overhead. This paper presents a hybrid instruction-set compiled simulation (HISCS) technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. This paper makes two important contributions: i) it improves the interpretive simulation performance by applying compiled simulation at the instruction level using a novel template customization technique to generate optimized decoded instructions during compile time; and ii) it reduces the compile time overhead by combining the benefits of both static and dynamic compiled simulation. Our experimental results using two contemporary processors (ARM7 and SPARC) demonstrate an order-of-magnitude reduction in compilation time as well as 70 % performance improvement on average over the best known published result in instruction-set simulation

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator. Comment: Submitted on behalf of EDAA (http://www.edaa.com/