Techniques de multiplexage pour un système d'émulation et de prototypage rapide à base de FPGA

This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit.De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit

Psychological responses of Tunisian general population during COVID-19 pandemic

Introduction: this is the first study assessing the psychological impact on Tunisian general population during the first peak of the COVID-19 pandemic. We aimed to assess the prevalence of anxiety, depressive symptoms and insomnia, as well as associated factors. Methods: a cross-sectional study was conducted through an online survey of 1615 people during March 23rd to May 5th, 2020. We used the hospital anxiety and depression scale for anxiety and depression screening, and the insomnia severity index to assess sleep disturbances. Results: our study revealed a high prevalence of anxiety and depressive symptoms, and insomnia (70.9%, 71.1% and 60.6% respectively). Multivariable statistics showed that anxiety symptoms were correlated to female gender (adjusted odds ratio [aOR] 1.784, 95% confidence interval (CI 1.252-2.542; p=10ˉ3), history of mental illness (aOR: 1.680, 95% CI: 1.329-2.125; p<10ˉ3), frequently social media exposure (aOR: 1.578, 95%CI: 1.250-1.992; p<10ˉ3), times to focus on COVID-19 ≥ 3hours (aOR: 1.840, 95% CI: 1.433-2.362; p<10ˉ3), consultation with doctor in the clinic in the past 14 days (aOR: 1.821, 95%CI :1.220-2.718; p=0.003) and recent traumatic event in the past 14 days (aOR: 1.641,95% CI: 1.331-2.024; p<10ˉ3). Principal factors associated with depressive symptoms included female gender (aOR: 1.637, 95% CI: 1.150-2.331; p=0.006), history of mental illness (aOR: 1.498, 95% CI: 1.189-1.888; p=10ˉ3), times to focus on COVID-19 ≥ 3hours (aOR: 1.956, 95% CI: 1.555-2.461; p<10ˉ3), and recent traumatic event in the past 14 days (aOR: 1.558, 95% CI: 1.265-1.919; p<10ˉ3). The main factors correlated to insomnia were younger (age <35years) (aOR: 1.592, 95% CI: 1.17 -2.152; p=0.003), female gender (aOR: 1.864, 95% CI: 1.252-2.775; p=0.002), having organic diseases (aOR: 1.527, 95% CI: 1.131-2.061; p=0.006), history of mental illness (aOR: 1.777, 95% CI: 1.396-2.263; p<10ˉ3), students (aOR: 1.931, 95% CI: 1.495-2.495; p<10ˉ3), times to focus on COVID-19 ≥3hours (aOR: 1.877, 95% CI: 1.467-2.400; p<10ˉ3) and recent traumatic event (aOR: 1.431, 95% CI: 1.144-1.789; p=0.002). Conclusion: our study revealed a major mental health burden in Tunisia during COVID-19 pandemic. Many factors were correlated to anxiety, depressive symptoms and insomnia, suggesting the need for greater psychological support in general and in certain vulnerable groups

The evolving SARS-CoV-2 epidemic in Africa: Insights from rapidly expanding genomic surveillance

INTRODUCTION Investment in Africa over the past year with regard to severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) sequencing has led to a massive increase in the number of sequences, which, to date, exceeds 100,000 sequences generated to track the pandemic on the continent. These sequences have profoundly affected how public health officials in Africa have navigated the COVID-19 pandemic. RATIONALE We demonstrate how the first 100,000 SARS-CoV-2 sequences from Africa have helped monitor the epidemic on the continent, how genomic surveillance expanded over the course of the pandemic, and how we adapted our sequencing methods to deal with an evolving virus. Finally, we also examine how viral lineages have spread across the continent in a phylogeographic framework to gain insights into the underlying temporal and spatial transmission dynamics for several variants of concern (VOCs). RESULTS Our results indicate that the number of countries in Africa that can sequence the virus within their own borders is growing and that this is coupled with a shorter turnaround time from the time of sampling to sequence submission. Ongoing evolution necessitated the continual updating of primer sets, and, as a result, eight primer sets were designed in tandem with viral evolution and used to ensure effective sequencing of the virus. The pandemic unfolded through multiple waves of infection that were each driven by distinct genetic lineages, with B.1-like ancestral strains associated with the first pandemic wave of infections in 2020. Successive waves on the continent were fueled by different VOCs, with Alpha and Beta cocirculating in distinct spatial patterns during the second wave and Delta and Omicron affecting the whole continent during the third and fourth waves, respectively. Phylogeographic reconstruction points toward distinct differences in viral importation and exportation patterns associated with the Alpha, Beta, Delta, and Omicron variants and subvariants, when considering both Africa versus the rest of the world and viral dissemination within the continent. Our epidemiological and phylogenetic inferences therefore underscore the heterogeneous nature of the pandemic on the continent and highlight key insights and challenges, for instance, recognizing the limitations of low testing proportions. We also highlight the early warning capacity that genomic surveillance in Africa has had for the rest of the world with the detection of new lineages and variants, the most recent being the characterization of various Omicron subvariants. CONCLUSION Sustained investment for diagnostics and genomic surveillance in Africa is needed as the virus continues to evolve. This is important not only to help combat SARS-CoV-2 on the continent but also because it can be used as a platform to help address the many emerging and reemerging infectious disease threats in Africa. In particular, capacity building for local sequencing within countries or within the continent should be prioritized because this is generally associated with shorter turnaround times, providing the most benefit to local public health authorities tasked with pandemic response and mitigation and allowing for the fastest reaction to localized outbreaks. These investments are crucial for pandemic preparedness and response and will serve the health of the continent well into the 21st century

Multiplexing techniques for FPGA-based emulation and prototyping platform

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit.This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit

Multiplexing techniques for FPGA-based emulation and prototyping platform

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit.This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit

Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing

International audienceIn multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on the number of inter-FPGA signals to share the same physical wire and be time-multiplexed. In this paper, we propose an adaptation of Pathfinder routing algorithm that minimizes the verification time of multi-FPGA systems by reducing the multiplexing ratio per physical wire. To run real experiments, we propose a large benchmark generation environment and we show that the verification system clock frequency is improved by 17% on average compared with conventional method

PufParkChain: Secure and Smart Parking Based on PUF Authentication and Lightweight Blockchain

Smart Parking Systems have emerged as a transformative solution to address the growing challenges associated with urbanization and increasing vehicular traffic. Such system integrates sensors, cameras, and other IoT connected devices to monitor parking spaces in real time. However, there are many security vulnerabilities in existing solutions, especially when it comes to car authentication at parking entry points. IoT sensors my be susceptible to Cyber-attacks and fraudulent activities, such as car theft, can exploit these vulnerabilities due to limited built-in security features. The reliability of authentication systems, based on IoT sensors can also be compromised by factors such as extreme weather conditions and physical damage. The cyber-physical solution we propose relies on Physical Unclonable Functions (PUFs) for identification and authentication in IoT devices to mitigate these challenges. The use of PUFs enhances the reliability and security of smart parking systems against unauthorized access and fraud. Furthermore, to ensure the integrity and confidentiality of the data within the smart parking ecosystem and to improve authentication process, we propose the implementation of a tailored blockchain framework. This framework incorporates lightweight local blockchains dedicated to individual parking slots, complemented by a central blockchain that manages data at the city level. The experimental results demonstrate the feasibility of the PUF computation process, showcasing an acceptable runtime for practical implementation. In the experimental results, we evaluated the SRAM used for the PUF implementation process and demonstrated its stability (intra HD equals to 2.25

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform

International audienceMulti-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm

Towards an Optimized Blockchain-Based Secure Medical Prescription-Management System

This work introduces a blockchain-based secure medical prescription-management system seamlessly integrated with a dynamic Internet of Things (IoT) framework. Notably, this integration constitutes a pivotal challenge in the arena of resource-constrained IoT devices: energy consumption. The choice of a suitable blockchain consensus mechanism emerges as the linchpin in surmounting this hurdle. Thus, this paper conducts a comprehensive comparison of energy consumption between two distinct consensus mechanisms: Proof of Work (PoW) and Quorum-based Byzantine fault tolerance (QBFT). Furthermore, an assessment of the most energy-efficient algorithm is performed across multiple networks and various parameters. This approach ensures the acquisition of reliable and statistically significant data, enabling meaningful conclusions to be drawn about the system’s performance in real-world scenarios. The experimental results show that, compared to the PoW, the QBFT consensus mechanism reduced the energy consumption by an average of 5%. This finding underscores the significant advantage of QBFT in addressing the energy consumption challenges posed by resource-constrained IoT devices. In addition to its inherent benefits of privacy and block time efficiency, the Quorum blockchain emerges as a more sustainable choice for IoT applications due to its lower power consumption