Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction

Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive body bias (ABB) techniques achieve the highest reduction in embedded systems energy dissipation [1]. In this paper we show that it is possible to produce comparable energy saving to that obtained using combined DVS and ABB techniques but with reduced hardware cost achieved by employing processing elements (PEs) with separate DVS or ABB capability. A co-synthesis methodology which is aware of tasks’ power-composition profile (the ratio of the dynamic power to the leakage power) is presented. The methodology selects voltage scaling capabilities (DVS, ABB, or combined DVS and ABB) for the PEs, maps, schedules, and voltage scales applications given as task graphs with timing constraints, aiming to dynamic and leakage energy reduction at low hardware cost. We conduct detailed experiments, including a real-life example, to demonstrate the effectiveness of our methodology. We demonstrate that it is possible to produce designs that contain PEs with only DVS or ABB technique but have energy dissipation that are only 4.4% higher when compared with the same designs that employ PEs with combined DVS and ABB capabilities

Variation aware analysis of bridging fault testing

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drive strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality

Manual measurement of retinal bifurcation features

This paper introduces a new computerized tool for accurate manual measurement of features of retinal bifurcation geometry, designed for use in investigating correlations between measurement features and clinical conditions. The tool uses user-placed rectangles to measure the vessel width, and lines placed along vessel center lines to measure the angles. An analysis is presented of measurements taken from 435 bifurcations. These are compared with theoretical predictions based on optimality principles presented in the literature. The new tool shows better agreement with the theoretical predictions than a simpler manual method published in the literature, but there remains a significant discrepancy between current theory and measured geometry

Photovoltaic sample-and-hold circuit enabling MPPT indoors for low-power systems

Photovoltaic (PV) energy harvesting is commonly used to power autonomous devices, and maximum power point tracking (MPPT) is often used to optimize its efficiency. This paper describes an ultra low-power MPPT circuit with a novel sample-and-hold and cold-start arrangement, enabling MPPT across the range of light intensities found indoors, which has not been reported before. The circuit has been validated in practice and found to cold-start and operate from 100 lux (typical of dim indoor lighting) up to 5000 lux with a 55cm2 amorphous silicon PV module. It is more efficient than non-MPPT circuits, which are the state-of-the-art for indoor PV systems. The proposed circuit maximizes the active time of the PV module by carrying out samples only once per minute. The MPPT control arrangement draws a quiescent current draw of only 8uA, and does not require an additional light sensor as has been required by previously-reported low-power MPPT circuits

Resource Aware Sensor Nodes in Wireless Sensor Networks

Wireless sensor networks are continuing to receive considerable research interest due, in part, to the range of possible applications. One of the greatest challenges facing researchers is in overcoming the limited network lifetime inherent in the small locally powered sensor nodes. In this paper, we propose IDEALS, a system to manage a wireless sensor network using a combination of information management, energy harvesting and energy monitoring, which we label resource awareness. Through this, IDEALS is able to extend the network lifetime for important messages, by controlling the degradation of the network to maximise information throughput

Energy managed reporting for wireless sensor networks

In this paper, we propose a technique to extend the network lifetime of a wireless sensor network, whereby each sensor node decides its individual network involvement based on its own energy resources and the information contained in each packet. The information content is ascertained through a system of rules describing prospective events in the sensed environment, and how important such events are. While the packets deemed most important are propagated by all sensor nodes, low importance packets are handled by only the nodes with high energy reserves. Results obtained from simulations depicting a wireless sensor network used to monitor pump temperature in an industrial environment have shown that a considerable increase in the network lifetime and network connectivity can be obtained. The results also show that when coupled with a form of energy harvesting, our technique can enable perpetual network operatio

Technical Report on Deploying a highly secured OpenStack Cloud Infrastructure using BradStack as a Case Study

Cloud computing has emerged as a popular paradigm and an attractive model for providing a reliable distributed computing model.it is increasing attracting huge attention both in academic research and industrial initiatives. Cloud deployments are paramount for institution and organizations of all scales. The availability of a flexible, free open source cloud platform designed with no propriety software and the ability of its integration with legacy systems and third-party applications are fundamental. Open stack is a free and opensource software released under the terms of Apache license with a fragmented and distributed architecture making it highly flexible. This project was initiated and aimed at designing a secured cloud infrastructure called BradStack, which is built on OpenStack in the Computing Laboratory at the University of Bradford. In this report, we present and discuss the steps required in deploying a secured BradStack Multi-node cloud infrastructure and conducting Penetration testing on OpenStack Services to validate the effectiveness of the security controls on the BradStack platform. This report serves as a practical guideline, focusing on security and practical infrastructure related issues. It also serves as a reference for institutions looking at the possibilities of implementing a secured cloud solution.Comment: 38 pages, 19 figures

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

High quality testing of grid style power gating

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test qualit