Analytical Model of the Forward Operation of 4H-SiC Vertical DMOSFET in the Safe Operating Temperature Range

A new analytical model of 4H-SiC DMOSFETs that is useful to explore their thermal stability is presented. The model is capable to describe, with closed form equations, the DC forward behavior of devices in a wide temperature range, including the effects of parasitic resistances and oxide interface traps. The model allows to analyze the on-set of electro-thermal stability of 4H-SiC DMOSFETs both in triode and in saturation region, and to monitor the impact of the series resistance and traps on reliable operation of devices. The accuracy of the model has been verified by comparisons with numerical simulations that evidence the effect of trap densities in the range [0-1014] cm-2eV-1 for operating temperatures up to 500K. Comparisons with experimental data of 1.2kV and 1.7kV commercial devices are used to validate the model

Photovoltaic Behavior of V 2 O 5 /4H-SiC Schottky Diodes for Cryogenic Applications

The photovoltaic behavior of (divanadioum pentoxide)/(4H polytype silicon carbide) Schottky diodes under ultraviolet illumination and down to 28K is investigated. In addition to their high stability, by using the thermionic model the analysis allows to confirm the predictability of performances at cryogenic temperatures, such as the high light/dark current ratio and the dependence of the photocurrent and open circuit voltage on material parameters. Because of the low-annealing temperature, this structure is shown to be a good candidate for solar-blind photodetectors in the UV spectral range of spatial and terrestrial cryogenic applications

Modification of amorphous and microcrystalline silicon film properties after irradiation with MeV and GeV protons

It is well known that the degree of crystallinity has a prominent influence on the stability of Silicon under proton irradiation. Amorphous silicon films are much more stable than mono- or polycrystalline silicon substrates or microcrystalline silicon thin films. In particular it has been shown, that in a micromorph tandem solar cell irradiated with protons in the lower MeV energy range only the microcrystalline diode showed a pronounced decrease in photocurrent after irradiation1. The proton irradiation induced damage in thick crystalline silicon samples has a maximum at beam energies between 1MeV and 4MeV and decreases for further increasing proton energies. However, irradiating an amorphous silicon/crystalline silicon heterojunction solar cell with a relatively dose of 24GeV, we observed a very strong drop in conversion efficiency with only minor recovery after sample annealing. In literature it has been reported 2, that the degradation of amorphous silicon is negligible for proton energies above 100MeV. In order to clarify to which extent also the thin film top layer of the hetero solar cell is affected by the proton irradiation, we exposed a variety of thin film silicon samples either to a 1.7MeV beam with a dose of 5.1012 protons/cm2 or to a 24GeV beam with a dose of 5 .1013 protons/cm2. The investigated intrinsic, p-type and n-type amorphous and microcrystalline silicon films have been deposited by conventional plasma deposition under variation of the silane / hydrogen gas phase ratio. Raman measurements have been done in order to determine the order of crystallinity obtained under various deposition conditions. We observed even at 24GeV a clear modification in the electrical characteristics of the films. Temperature dependent measurements of the dark current revealed in particular for all doped samples a significant increase of the activation energy, that might be explained by a decrease of the dopant efficiency, while for intrinsic a-Si:H layers the increasing activation energy is due to deep defect creation

Multiplierless coprocessor for difference of Gaussian (DOG) calculation

A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures

High Speed CAVLC Encoder Suitable for Field Programmable Platforms

In this paper a new Context-Adaptive Variable- Length Coding encoder is proposed particularly aimed to be implemented with Field Programmable Logics. The design employs redundant circuitry to implement priority cascading logics which allows to highly improve its degree of parallelism, while the area cost related to the unavoidable replication of logic blocks has been balanced by means of arithmetic manipulations capable to eliminate some of the most area demanding tables of variable-length codewords. The proposed design is capable to process 1080p@30 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost, lowspeed FPGA

SiO2/4H-SiC interface traps effects on the input capacitance of DMOSFET

In this paper, an analytical model is presented to describe the input capacitance of Power-MOSFETs in 4H polytype of Silicon Carbide (4H-SiC). In order to provide an instrument for accurate interpretations of C-V measurements and for a deeper understanding of the device operations, the model describes the charge variations induced by the presence of the oxide-semiconductor interface trapped charge. Their energy dependence has been accounted to describe the charge dynamics into the channel and the accumulation layer and proved by comparisons with numerical simulations

An Area Reduced Design of the Context-Adaptive Variable-Length Encoder Suitable for Embedded Systems

In this paper a new Context-Adaptive Variable Length Coding (CAVLC) encoder architecture is proposed aimed to be implemented in embedded systems and field programmable logic. The design proposes novel Arithmetic Table Elimination (ATE) techniques, along with a table compression technique applied to those tables that cannot be eliminated by arithmetic manipulations. These approaches allows to halve the total number of tables requested by CAVLC algorithm and bring to an overall memory saving of about 87% with respect to an unoptimized implementation of the tables. Computational performances of the encoder have been improved by increasing the degree of parallelism through the use of priority cascading logic. With the proposed approaches the CAVLC encoder is capable of real time compression of 1080p HDTV video streams, coded in YCbCr 4:2:0, when it is implemented with a low-end Xilinx Spartan 3 FPGA, where the encoder achieves an operation frequency of 63MHz and requires an area occupancy of 2200 LUTs