Copper wafer bonding in three-dimensional integration

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.Includes bibliographical references (p. 165-176).Three-dimensional (3D) integration, in which multiple layers of devices are stacked with high density of interconnects between the layers, offers solutions for problems when the critical dimensions in integrated circuits keep shrinking. Copper wafer bonding has been considered as a strong candidate for fabrication of three-dimensional integrated circuits (3-D IC). This thesis work involves fundamental studies of copper wafer bonding and bonding performance of bonded interconnects. Copper bonded wafers exhibit good bonding qualities and present no original bonding interfaces when the bonding process occurs at 400⁰C/4000 mbar for 30 min, followed by nitrogen anneal at 400⁰C for 30 min. Oxide distribution in the bonded layer is uniform and sparse. Evolution of microstructure morphologies and grain orientations of copper bonded wafers during bonding and annealing were studied. The bonded layer reaches steady state after post-bonding anneal. The microstructure morphologies and bond strengths of copper bonded wafers under different bonding conditions were investigated.A map summarizing these results provides a useful reference on process conditions suitable for three-dimensional integration based on copper wafer bonding. Similar microstructure morphology of copper bonded interconnects was observed to that of copper bonded wafers. Specific contact resistances of bonded interconnects of approximately 10⁻⁸ [ohms]-cm² were measured by using a novel test structure which can eliminate the errors from misalignment during bonding. The bonding qualities of different interconnect sizes and densities have been investigated. In addition to increasing the bonding temperature and duration, options such as larger interconnect sizes, total bonding area, or use of dummy pads for bonding in the unused area improve the quality of bonded interconnects. Process development of silicon layer stacking based on Cu wafer bonding was successfully applied to demonstrate a strong four-layer-stack structure.Bonded Cu layers in this structure become homogeneous layers and do not show original bonding interfaces. This process can be reliably applied in three-dimensional integration applications.by Kuan-Neng Chen.Ph.D

The 2nd Workshop on Maritime Computer Vision (MaCVi) 2024

The 2nd Workshop on Maritime Computer Vision (MaCVi) 2024 addresses maritime computer vision for Unmanned Aerial Vehicles (UAV) and Unmanned Surface Vehicles (USV). Three challenges categories are considered: (i) UAV-based Maritime Object Tracking with Re-identification, (ii) USV-based Maritime Obstacle Segmentation and Detection, (iii) USV-based Maritime Boat Tracking. The USV-based Maritime Obstacle Segmentation and Detection features three sub-challenges, including a new embedded challenge addressing efficicent inference on real-world embedded devices. This report offers a comprehensive overview of the findings from the challenges. We provide both statistical and qualitative analyses, evaluating trends from over 195 submissions. All datasets, evaluation code, and the leaderboard are available to the public at https://macvi.org/workshop/macvi24.Comment: Part of 2nd Workshop on Maritime Computer Vision (MaCVi) 2024 IEEE Xplore submission as part of WACV 202

Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications

The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV substrates needs to be carefully investigated. The changing in TSV size under the same TSV aspect ratio does not obviously affect the stress toward the surroundings. On the other hand, the adjustment on TSV aspect ratios results in different stress values, and the aspect ratio of 1:8 results in the largest stress in the analysis. Besides, the annealing temperature has more influence on the stress than the size of TSV. As a consequence, reduction on the annealing temperature is an effective method to achieve a low stress for TSV in HBM stacks. Therefore, several methods for low temperature hybrid bonding have also been reviewed and discussed