Catalytic Reactive Distillation for the Esterification Process: Experimental and Simulation

In the present study, methyl acetate has been synthesized using esterification of acetic acid with methanol in a continuous packed bed catalytic reactive distillation column in the presence of novel Indion 180 ion exchange resin solid catalyst. The experiments were conducted at various operating conditions like reboiler temperature, reflux ratio, and different feed flow rates of the acetic acid and methanol. The non-ideal pseudo-homogeneous kinetic model has been developed for esterification of acetic acid with methanol in the presence of Indion 180 catalyst. The developed kinetic model was used for the simulation of the reactive distillation column for the synthesis of methyl acetate using equilibrium stage model in Aspen Plus version 7.3. The simulation results were compared with experimental results, and found that there is a good agreement between them. The sensitivity analyses were also carried out for the different parameters of bottom flow rate, feed temperatures of acetic acid and methanol, and feed flow rate of acetic acid and methanol. This work is licensed under a Creative Commons Attribution 4.0 International License

Water-saving Rice Production Technologies in Krishna Western Delta Command of Andhra Pradesh – An Economic Analysis

The economic analysis of water-saving rice production technologies, viz. system of rice intensification (SRI), semi-dry and rotational irrigation vis-à-vis farmers’ practice has been carried out based on the study executed in Modukuru pilot area of Guntur district of Andhra Pradesh. Among the three water-saving rice production technologies analyzed, the total cost of cultivation has been recorded highest in SRI (Rs 58645/ha), followed by rotational (Rs 47140/ha) and semi-dry (Rs 39321/ha). But, the per hectare yield has been found highest in SRI (6.85 t), followed by semi-dry (6.66 t) and rotational (6.2 t), inferring that all the three technologies have recorded higher yields over farmers’ practice of 5.5 t/ha. However, the net returns and B-C ratio are maximum in semi-dry (Rs 43,484/ha; 1.11), followed by rotational (Rs 30,085; 0.64) and SRI (Rs 26,466/ha; 0.45) methods. Similarly, the water-use efficiency has been found highest in SRI (8.53 kg/ ha-mm), followed by semi-dry (8.02 kg/ha-mm) and rotational (7.33 kg/ ha-mm) methods, while the water-use efficiency benefit (Rs/ha-mm) has been recorded maximum in semi-dry (52.39), followed by SRI (42.08) and rotational (35.56) methods. With the initiation of Andhra Pradesh Water Management Project, Bapatla, the area under semi-dry rice cultivation has been found increasing over a period of four years, from 0.6 ha in 2004-2005 to 22 ha in 2007 -2008.Agricultural and Food Policy,

MAXIMUM DATA RATE DETERMINATION OF A TELEPHONE TRANSMISSION CHANNEL

The transmission channel is an electrical medium that bridges the distance from the source to the destination. It may be apair of wires, a coaxial cable, a radio path, or an optical fiber. Every channel introduces some amount of transmission loss orattenuation and, therefore, the transmitted power progressively decreases with increasing distance. The signal is alsodistorted in the transmission channel because of different attenuation at different frequencies. Signals usually containcomponents at many frequencies and if some are attenuated and some are not, the shape of the signal changes. This change isknown as distortion. Note that a transmission channel often includes many speech or data channels that are multiplexed intothe same cable pair or fiber. In this paper we present the determination of maximum data rate of a telephone channel.Keywords: Bandwidth, Data Rate, Symbol Rate, Transmission Channe

4-Chloro-N-(3-chloro­phen­yl)benzamide

The title compound, C13H9Cl2N, has an intra­molecular C—H⋯O close contact, and presents the NH group syn to the meta-chloro group in the aniline ring and trans to the C=O group. The crystal packing is formed by infinite chains of N—H⋯O hydrogen bonds along the c axis. Cl⋯Cl [3.474 (1) Å] contacts link chains. The crystal used for data collection was a twin, the domains related by the twin law 0.948 (1)/0.052 (1)

Barriers to Sustainable Waste Management in Mountain Tourism: Evidence from India

Goal 15 of the Sustainable Development Goals calls for efforts to protect fragile mountain ecosystems. Waste generated due to mountain tourism leads to environmental degradation, biodiversity loss, and poses a significant challenge to achieving this goal. Mountains which are characterized by uninhabitable terrain and remoteness, coupled with current tourism practices compound this challenge. The paper resolves this challenge by understanding barriers to sustainably manage waste using th Classical DEMATEL method. Based on data from 36 experts in India’s mountain tourism industry, barriers to sustainable management of non-biodegradable waste are analyzed. Results suggest that enforcement of regulations, waste collection infrastructure, and lack of transportation for waste transfer are the most prominent barriers that can be mitigated by collectively leveraging four tangible barriers: tourists’ motivation or achievement mentality, local government’s initiative, economic value of waste, and tourists’ lack of environmental awareness. Based on this, a policy intervention mandating certification standards for tourists is suggested before they embark on mountain tourism

Preparation of lithium 5-lithiomethy-3-methylpyrazole-1-carboxylate and its reaction with α-oxoketene dithioacetals: a new general method for substituted and annelated pyrazolo[1,5-a]pyridines

5-Methylpyrazole derivative 1 is metallated at the C-5 methyl carbon atom to form lithium 5-lithiomethyl-3-methylpyrazole-1-carboxylate 3 which on reaction with α-oxoketene dithioacetals 4a-d, 12a-c and 15a-b yields substituted and annelated pyrazolo[1,5-a]pyridines 7a-d, 13a-c and 16a-b

Circuit Design of Programmable Logic and Interconnect Blocks using Spin Transfer Torque RAM for Non-Volatile FPGAs

Most of the Field-Programmable Gate Arrays (FPGAs) are currently SRAM based. The conventional SRAM has been the primary choice for memory storage in the Configurable Logic Blocks (CLBs) as well as for the configuration bits of the reconfigurable interconnects. However SRAM based FPGAs are volatile and needs an external non-volatile memory to store the configuration data. Also SRAM leakage currents increases as technology scales towards lower nodes. The use of non-volatile memories such as Spin-Transfer Torque (STT)-RAM helps to overcome the drawbacks of SRAM-based FPGAs without significant speed penalty. In this paper we present the design of simple non-volatile CLBs using STT-RAM technology. For verifying the design these CLBs have been programmed to implement various functions. The design has been simulated and verified using cadence tools in CMOS 40nm technology

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated