Comparison of Electrical Characteristics between Bulk MOSFET and Silicon-on-Insulator (SOI) MOSFET

Conventional MOSFET has already passed lower than 45nm transistorfabrication. As silicon is now hitting the atomic resolution and reaching its physical and electrical limitation, producing a proper working transistor tends to be more difficult and complicated. The major challenge is to fabricate a transistor with anominal threshold voltage (VTH), lower gate leakage current (IOFF) and lower drain induced barrier lowering (DIBL). To overcome these problems, Siliconon-insulator (SOI) MOSFET has been proposed, and it is believed to be capable of suppressing short channel effects (SCEs) by burying oxide layer in the silicon substrate. ATHENA and ATLAS module of SILVACO software were used in simulating the virtual fabrication and electrical performance of the transistors. An investigation on the characteristics and performance of the devices has been conducted in order to compare their electrical characteristics. The MOSFETstructure was constructed byutilizingSILVACO Athenamodule,and the electrical characteristicswere simulated using SILVACO Atlas module. The results of boththe conventional bulk MOSFET and the SOI MOSFETwere analyzed. It was observed that SOI MOSFET was superior compared to the conventional MOSFET interms of their overallelectrical characteristic

Optimization of Electrical Properties in TiO2/WSix-based Vertical DG-MOSFET using Taguchi-based GRA with ANN

This study describes a proposed method to determine the most optimal level of process parameters, considering multiple electrical properties of titanium dioxide/tungsten silicide (TiO2/WSix)-based vertical double-gate MOSFET. The proposed method utilizes a combination of the L9 orthogonal array (OA) of Taguchi-based grey relational analysis (GRA) and the artificial neural network (ANN). The VTH implant energy, halo implant dose, source/drain (S/D) implant dose and S/D implant tilt angle are the selected processs parameters to be optimized for the optimal value of on-current (ION), off-current (IOFF) and subthreshold slope (SS). The design of experiment (DoE) is based on the L9 OA of Taguchi method and the experimental value for multiple electrical properties are converted into a grey relational grade (GRG). The well-trained ANN based on the Levenberg-Marquardt algorithm is developed to predict the best optimization results. The most optimal level of four process parameters towards ION, IOFF and SS are selected based on the highest GRG predicted by welltrained ANN. The most optimal value for ION, IOFF and SS after the optimization are observed to be 1612.1 µA/µm, 8.801E-10 A/µm and 67.74 mV/dec respectively with 0.7417 of predicted GRG

Implementation of Taguchi Modeling for Higher Drive Current (ION) in Vertical DG-MOSFET Device

Vertical Double-Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is capable to minimize various short channel effect (SCEs) problems. Vertical DG-MOSFET is constructed by having two gates that are able to control the channel from both sidesand has better electrostatic control over the channel. Meanwhile, the drive current (ION) should be maintained above 0.2mA in order to decide the driving capability of the device. The drive current (ION) must be set at high value so that the transistor acquires superb driving characteristicsthat are capable to switch the device into on-state condition. This paper describes the design of a vertical DGMOSFET, while keeping the drive current (ION) as maximum as possible, by utilizing both SILVACO TCAD software and statistical methods. Based on the ANOVA method, factor E (Halo Implant Energy –45%), factor F (Halo Implant Tilt –22%) and factor L (Compensation Implant Energy – 15.78%) were recognized as the most significant factors. The maximum value of drive current (ION) was observed to be at 0.3291 mA/µm with signal-to-noise ratio of -10.00dB

Application of Taguchi-based Grey Fuzzy Logic for Simultaneous Optimization in TiO2/WSix-based Vertical Double-gate MOSFET

This present study focuses on finding the optimal process parameters, considering multiple electrical properties of titanium dioxide/tungsten silicide (TiO 2 /WSi x )-based vertical double-gate MOSFET via L 9 orthogonal array (OA) Taguchibased grey fuzzy logic. Four process parameters that are V TH implant energy, halo implant dose, source/drain (S/D) implant dose and S/D implant tilt angle, are optimized to obtain the most desired value of on-current (I ON ), off-current (IOFF ) and subthreshold slope (SS). The design of experiment (DoE) is based on the L 9 OA of Taguchi method and the experimental value for multiple electrical characteristics are represented by a grey fuzzy reasoning grade (GFRG). The most optimal level of four process parameters towards I ON , IOFF and SS are chosen based on the highest GFRG. The results of analysis of variance (ANOVA) show that the most dominant process parameter is S/D implant tilt angle with 96.76% factor effect on GFRG. The most optimal value for ION , IOFF and SS after the optimization are 1589.2 µA/µm, 8.483E-10 A/µm and 68.21 mV/dec respectively with 0.564 of GFRG

Characterization & Optimization of 32nm P-Channel MOSFET Device

In this paper, effect of the process parameters variation on response characteristics such as threshold voltage (VTH) in 32nm p-channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) device was investigated. An orthogonal array, signal-to noise (S/N) ratio and analysis of variance were employed to studythe performance characteristics of the p-channel device. The control factors were used in this research are oxide growth temperature, VTH implant energy, Source/Drain (S/D) implant dose and compensation implant energy. The fabrication of the transistor device was performed using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. In pchannel device, VTHimplant energy (57%) was identified as one of the control factor that has the strongest effect on the threshold voltage.The result shows that the VTHvalue has least variance and percent different from the target value (-0.289V) for this device is 3.11% (-0.280V). As conclusions, setting up design of experiment with the Taguchi Method of L9 orthogonal arrays and TCAD simulator, the optimal solution for the robust design recipe of 32nm p-channel device was successfully achieved

Analyze Of Process Parameter Variance In 19nm Wsi2/Tio2 NMOS Device Using 2k-Factorial Design

This project investigates and analyzes the impact of process parameter variance on the drive current (ION) and leakage current (IOFF) for 19nm WSi2/TiO2 NMOS device using 2k-factorial design. The four process parameter, namely halo implant dose, halo implant energy, source/drain (S/D) implant dose and S/D implant energy will be investigated and adjusted to improve the results. The simulated of the device was performed by using ATHENA module. Meanwhile the electrical characterization of the device was implemented by using ATLAS module. These two modules will be combined with 2kfactorial to aid design and optimize the process parameters. The most effective process parameter with respect ION and IOFF were chosen depending on the percentage of the factor effect on S/N ratio that indicates the relative power of factor to reduce variation. The most dominant or significant factors in S/N Ratio are pocket halo implant dose and S/D implant energy. Meanwhile, the values of ION and IOFF values for 19nm WSi2/SiO2 NMOS device after optimization approaches are 591.38 µA/µm and 2.217 pA/µm respectively. The results obtained are meet the requirement of International Technology Roadmap Semiconductor (ITRS) 2013 prediction