Rate-Constrained Wireless Networks with Fading Channels: Interference-Limited and Noise-Limited Regimes

A network of $n$ wireless communication links is considered in a Rayleigh fading environment. It is assumed that each link can be active and transmit with a constant power $P$ or remain silent. The objective is to maximize the number of active links such that each active link can transmit with a constant rate $\lambda$. An upper bound is derived that shows the number of active links scales at most like $\frac{1}{\lambda} \log n$. To obtain a lower bound, a decentralized link activation strategy is described and analyzed. It is shown that for small values of $\lambda$, the number of supported links by this strategy meets the upper bound; however, as $\lambda$ grows, this number becomes far below the upper bound. To shrink the gap between the upper bound and the achievability result, a modified link activation strategy is proposed and analyzed based on some results from random graph theory. It is shown that this modified strategy performs very close to the optimum. Specifically, this strategy is \emph{asymptotically almost surely} optimum when $\lambda$ approaches $\infty$ or 0. It turns out the optimality results are obtained in an interference-limited regime. It is demonstrated that, by proper selection of the algorithm parameters, the proposed scheme also allows the network to operate in a noise-limited regime in which the transmission rates can be adjusted by the transmission powers. The price for this flexibility is a decrease in the throughput scaling law by a multiplicative factor of $\log \log n$.Comment: Submitted to IEEE Trans. Information Theor

How much feedback is required in MIMO Broadcast Channels?

In this paper, a downlink communication system, in which a Base Station (BS) equipped with M antennas communicates with N users each equipped with K receive antennas ($K \leq M$), is considered. It is assumed that the receivers have perfect Channel State Information (CSI), while the BS only knows the partial CSI, provided by the receivers via feedback. The minimum amount of feedback required at the BS, to achieve the maximum sum-rate capacity in the asymptotic case of $N \to \infty$ and different ranges of SNR is studied. In the fixed and low SNR regimes, it is demonstrated that to achieve the maximum sum-rate, an infinite amount of feedback is required. Moreover, in order to reduce the gap to the optimum sum-rate to zero, in the fixed SNR regime, the minimum amount of feedback scales as $\theta(\ln \ln \ln N)$, which is achievable by the Random Beam-Forming scheme proposed in [14]. In the high SNR regime, two cases are considered; in the case of $K < M$, it is proved that the minimum amount of feedback bits to reduce the gap between the achievable sum-rate and the maximum sum-rate to zero grows logaritmically with SNR, which is achievable by the "Generalized Random Beam-Forming" scheme, proposed in [18]. In the case of $K = M$, it is shown that by using the Random Beam-Forming scheme and the total amount of feedback not growing with SNR, the maximum sum-rate capacity is achieved.Comment: Submitted to IEEE Trans. on Inform. Theor

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call