Defect-tolerance and testing for configurable nano-crossbars

Moore\u27s Law speculated a trend in computation technology in terms of number of transistors per unit area that would double roughly every two years. Even after 40 years of this prediction, current technologies have been following it successfully. There are however, certain physical limitations of current CMOS that would result in fundamental obstructions to continuation of Moore\u27s Law. Although there is a debate amongst experts on how much time it would take for this to happen, it is certain that some entirely new paradigms for semiconductor electronics would be needed to replace CMOS and to delay the end of Moore\u27s Law. Silicon nanowires (SiNW) and Carbon nanotubes (CNT) possess significant promise to replace current CMOS --Abstract, page iv

A BIST Approach for Configurable Nanofabric Arrays

This work proposes a Built-in Self Test (BIST) approach to test crossbars for a defined set of faults. The BIST can classify the different programmable elements in the crossbars as non-defective or defective with a certain fault type. The logic synthesis can then configure the crossbar by avoiding these defective elements

Nanofabric PLA Architecture with Double Variable Redundancy

It has been shown that fundamental electronic structures such as Diodes, and FET\u27s can be constructed using selectively doped semiconducting carbon nanotubes or silicon nanowires (CNT\u27s, SiNW\u27s) at nanometer scale. Memory and Logic cores using these technologies have been proposed, that use the configurable junctions in two-dimensional crossbars of CNT\u27s. These memories and logic arrays at this scale exhibit significant amount of defects that account for poor yield. Configuration of these devices in presence of defects demands for an overhead in terms of area and programming time. In this work, we introduce a PLA (programmable logic array) configuration that makes use of design-specific redundancy in terms of number of nanowires, in order to simplify the process of programming the PLA, increase the yield and reduce the time complexity and in turn, the cost of the system

NCL Implementation of Dual-Rail 2\u3csup\u3eS\u3c/sup\u3e Complement 8x8 Booth2 Multiplier using Static and Semi-Static Primitives

In this work, we use static and semi-static versions of NULL Convention Logic (NCL) primitives (i.e., threshold gates) to implement a dual-rail 8times8 2s complement multiplier using the Modified Booth2 algorithm for partial product generation and a Wallace tree for partial product summation. We establish the multiplier\u27s functionality utilizing VHDL-based simulations of the gate-level structural design. The design is then implemented at the transistor-level and layout-level using both static and semi-static threshold gates, for a 1.8V 0.18mum TSMC CMOS process; and these two implementations are compared in terms of area, power, and speed

Nanofabric PLA Architecture with Flexible Nanowire-Redundancy

It has been shown that fundamental electronic structures such as Diodes, and FET\u27s can be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNT\u27s, SiNWs) at nanometer scale. Memory and Logic cores using these technologies have been proposed, that use the configurable junctions in two-dimensional crossbars of CNT\u27s. These Memories and Logic Arrays at this scale exhibit significant amount of defects that account for poor yield. Configuration of these devices in presence of defects demands for an overhead in terms of area and programming time. in this work, we introduce a PLA configuration that makes use of design-specific redundancy in terms of number of nanowires, in order to simplify the process of programming the PLA, increase the yield and reduce the time complexity and in turn, the cost of the system

Analysis of dominant flow structures and their flow dynamics in chemical process equipment using snapshot proper orthogonal decomposition technique

Snapshot proper orthogonal decomposition (POD) technique has been applied to reveal the dominant flow structures, their dynamics and length scales in six widely used industrial equipments (stirred tank, bubble column, Taylor-Couette flow (annual contactor), ultrasonic reactor, jet reactor, and channel flow). The variation in length scale of structures within an equipment, with change in its operating conditions (Reynolds number and power input) or change in its geometric configuration (sparger and impeller designs), has been brought out in this work. The planar data set for POD analysis was obtained from particle image velocimetry (PIV) and large eddy simulation (LES) studies. The dominant spatial topology was analyzed by using the velocity and vorticity POD modes. The modes have revealed the following flow structures: the ascending streaks and bursts in channel flow, the vortex tube and leading edge vortices in jets, the irregular small chaotic vortices in Taylor-Couette flow, the variation in plume oscillation and flow structures in the vortical region of bubble column resulting from changes in sparger design, the high intensity vortices near the source of ultrasound in the ultrasonic reactor and the effect of impeller designs on dominant flow structures and near blade vortices in the stirred tank. The length scales of structures are obtained by applying image processing on the spatial modes. The dynamics of these flow structures in each of the items of equipment is captured by reconstructing the flow field using appropriate spatial and temporal modes that contribute to these structures. Further, a unique attempt has been made to correlate the length scale distribution with the mixing time

Nanofabric PLA architecture with Redundancy Enhancement

Fundamental electronic structures such as Diodes and FETs have been shown to be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNTs, SiNWs) at nanometer scale. Memory and Logic cores have been proposed, that use the configurable junctions in 2-D crossbars of CNTs. These Memory and Logic arrays at this scale exhibit a significant amount of defects that account for poor a yield. Configuration of these devices in the presence of defects demands an overhead in terms of area and programming time. This work introduces a PLA configuration that makes use of fixed and adaptive redundancy in terms of the number of nanowires. This is done in order to simplify the process of programming the PLA, increase the yield, reduce the time complexity, and in turn, reduce the cost of the system. © 2007 IEEE

Nanowire Crossbar PLA with Adaptive Variable Redundancy

Fundamental electronic structures such as Diodes and FETs have been shown to be constructed using selectively doped semiconducting Carbon Nanotubes or Silicon Nanowires (CNTs, SiNWs) at nanometer scale. Memory and Logic cores s have been proposed, that use the configurable junctions in 2-D crossbars of CNTs. These Memory and Logic arrays at this scale exhibit a significant amount of defects that account for poor a yield. Configuration of these devices in the presence of defects demands an overhead in terms of area and programming time. This work introduces a PLA configuration that makes use of design-specific redundancy in terms of the number of nanowires. This is done in order to simplify the process of programming the PLA, increase the yield, reduce the time complexity, and in turn, reduce the cost of the system

CFD simulation of bubble column- an analysis of interphase forces and turbulence models

3D transient CFD simulations of bubble column have been performed for a wide range of superficial gas velocity on an industrially relevant cylindrical column and the CFD predictions have been compared with the experiments of Menzel et al. [T. Menzel, T. Weide, O. Staudacher, U. Onken, Reynolds stress model for bubble column reactor, Ind. Eng. Chem. Res. 29 (1990) 988-994]. Simulations have also been performed to understand the sensitivity of different interphase forces (drag, lift, turbulent dispersion and added mass). This work highlights the importance of choosing the C<SUB>L</SUB> value and the drag law in accordance with the bubble size. Further, a laboratory scale bubble column with three different spargers (perforated plate, sintered plate and single hole) has been simulated using three different turbulence closure (k-ε , RSM and LES) models, with the purpose of critically comparing their predictions with experimental data [M.R. Bhole, S. Roy, J.B. Joshi, Laser doppler anemometer measurements in bubble column: effect of sparger, Ind. Eng. Chem. Res. 45 (26) (2006) 9201-9207; A.A. Kulkarni, K. Ekambara, J.B. Joshi, On the development of flow pattern in a bubble column reactor: experiments and CFD, Chem. Eng. Sci. 62 (2007) 1049-1061]. It has been found that the RSM shows better agreement than the k-ε model in predicting the turbulent kinetic energy profiles. Comparatively, the LES has been successful in capturing the averaged behavior of the flow, while at some locations; it slightly over predicts the kinetic energy profiles. Further, it has been able to simulate the instantaneous vortical-spiral flow regime in case of sieve plate column, as well as, the bubble plume dynamics in case of single hole sparger. Thus, LES can be effectively used for study of flow structures and instantaneous flow profiles

A BIST Technique for Configurable Nanofabric Arrays

This work proposes a built-in self test (BIST) approach to test crossbars for a defined set of faults. The BIST can classify the different programmable elements in the crossbars as non-defective or defective with a certain fault type. The logic synthesis can then configure the crossbar by avoiding these defective elements