Multistage adaptive noise cancellation and multi-dimensional signal processing for ultrasonic nondestructive evaluation

Ultrasonic signal processing presents several challenges with respect to both noise removal and interpretation. The interference of unwanted reflections from material grain structure can render the data extremely noisy and mask the detection of small flaws. It is therefore imperative to separate the flaw reflections from grain noise. The interpretation or classification of ultrasonic signals in general is relatively difficult due to the complexity of the physical process and similarity of signals from various classes of reflectors;Adaptive noise cancellation techniques are ideally suited for reducing spatially varying noise due to the grain structure of material in ultrasonic nondestructive evaluation. In this research, a multi-stage adaptive noise cancellation (MANC) scheme is proposed for reducing spatially varying grain noise and enhancing flaw detection in ultrasonic signals. The overall scheme is based on the use of an adaptive least mean square error (LMSE) filter with primary and reference signals derived from two adjacent positions of the transducers. Since grain noise is generally uncorrelated, in contrast to the correlated flaw echoes, adaptive filtering algorithms exploit the correlation properties of signals in a C-scan image to enhance the signal-to-noise ratio (SNR) of the output signal;A neural network-based signal classification system is proposed for the interpretation of ultrasonic signals obtained from inspection of welds, where signals have to be classified as resulting from porosity, slag, lack of fusion, or cracks in the weld region. Standard techniques rely on differences in individual A-scans to classify the signals. This thesis investigates the need for investigating signal features that incorporate the effects of beam spread and echo dynamics. Such effects call for data interpretation schemes that include a neighborhood of A-scans carrying information about a reflector. Several ultrasonic signal features based on the information in a two-dimensional array of ultrasonic waveforms, ranging from the estimation of statistical characteristics of signals to two and three-dimensional transform-based methods, are evaluated. A two-dimensional scan of ultrasonic testing is also represented in the form of images (B- and B\u27-scans). Multidimensional signal and image-processing algorithms are used to analyze the images. Two and three-dimensional Fourier transforms are applied to ultrasonic data that are inherently three-dimensional in nature (2 spatial and 1 time). A variety of transform-based features are then utilized for obtaining the final classification

Competition between structural distortion and magnetic moment formation in fullerene C20_{20}

We investigated the effect of on-site Coulomb interactions on the structural and magnetic ground state of the fullerene C$_{20}$ based on density-functional-theory calculations within the local density approximation plus on-site Coulomb corrections (LDA+$U$). The total energies of the high symmetry ($I_{h}$) and distorted ($D_{3d}$) structures of C$_{20}$ were calculated for different spin configurations. The ground state configurations were found to depend on the forms of exchange-correlation potentials and the on-site Coulomb interaction parameter $U$, reflecting the subtle nature of the competition between Jahn-Teller distortion and magnetic instability in fullerene C$_{20}$. While the non-magnetic state of the distorted $D_{3d}$ structure is robust for small $U$, a magnetic ground state of the undistorted $I_{h}$ structure emerges for $U$ larger than 4 eV when the LDA exchange-correlation potential is employed.Comment: 4 figures, 1 tabl

Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware

Spiking Neural Networks (SNNs) have high potential to process information efficiently with binary spikes and time delay information. Recently, dedicated SNN hardware accelerators with on-chip synapse memory array are gaining interest in overcoming the limitations of running software-based SNN in conventional Von Neumann machines. In this paper, we proposed an efficient synapse memory structure to reduce the amount of hardware resource usage while maintaining performance and network size. In the proposed design, synapse memory size can be reduced by applying presynaptic weight scaling. In addition, axonal/neuronal offsets are applied to implement multiple layers on a single memory array. Finally, a transposable memory addressing scheme is presented for faster operation of spike-timing-dependent plasticity (STDP) learning. We implemented a SNN ASIC chip based on the proposed scheme with 65 nm CMOS technology. Chip measurement results showed that the proposed design provided up to 200X speedup over CPU while consuming 53 mW at 100 MHz with the energy efficiency of 15.2 pJ/SOP

Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware

Spiking Neural Networks (SNNs) have high potential to process information efficiently with binary spikes and time delay information. Recently, dedicated SNN hardware accelerators with on-chip synapse memory array are gaining interest in overcoming the limitations of running software-based SNN in conventional Von Neumann machines. In this paper, we proposed an efficient synapse memory structure to reduce the amount of hardware resource usage while maintaining performance and network size. In the proposed design, synapse memory size can be reduced by applying presynaptic weight scaling. In addition, axonal/neuronal offsets are applied to implement multiple layers on a single memory array. Finally, a transposable memory addressing scheme is presented for faster operation of spike-timing-dependent plasticity (STDP) learning. We implemented a SNN ASIC chip based on the proposed scheme with 65 nm CMOS technology. Chip measurement results showed that the proposed design provided up to 200X speedup over CPU while consuming 53 mW at 100 MHz with the energy efficiency of 15.2 pJ/SOP.110Ysciescopu

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta???sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and low-power is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively