Gravitino Problem in Inflation Driven by Inflaton-Polonyi K\"ahler Coupling

We discuss the cosmological gravitino problem in inflation models in which the inflaton potential is constructed from K\"ahler potential rather than superpotential: a representative model is $\overline{\text{D}3}$-induced geometric inflation. A critical ingredient in this type of models is the coupling of the inflaton and Polonyi (supersymmetry-breaking) field in the K\"ahler potential, which is needed to build the inflaton potential. We point out the same coupling let the inflaton dominantly decay into a pair of inflatino and gravitino causing the gravitino problem. We propose some possible solutions to this problem.Comment: 14 pages; accepted by PLB, title and abstract changed to clarify the topic, conclusion not changed, references adde

Mutual Inductance Measurement for Power Device Package Using Time Domain Reflectometry

Stray inductance inside power device package will be a constraint on improvement of power density as well as switching frequency in power converters because the converters will suffer from electromagnetic interference (EMI)-related problems. This paper proposes a measurement method of mutual inductance for power device packages using time domain reflectometry. The method is characterized by introducing four-terminal measurement that distinguishes self and mutual inductances among collector, emitter, and gate terminals. A measurement fixture for a discrete IGBT is designed, constructed, and tested to ensure repeatability of the proposed method. Experimental results verifies the viability of the proposed method.2016 IEEE Energy Conversion Congress and Exposition (ECCE), 18-22 September 2016, Milwaukee, WI, US

A New Evaluation Circuit with a Low-Voltage Inverter Intended for Capacitors Used in a High-power Three-phase Inverter

DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter.2016 IEEE Applied Power Electronics Conference and Exposition (APEC 2016), March 20-24, 2016, Long Beach, California, US

Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter

DC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current-rating and full-scale voltage-rating inverter. Theoretical analysis and simulated results verify the effectiveness of new evaluation circui

A New Evaluation Circuit with a Low-Voltage Inverter Intended for Capacitors Used in a High-power Three-phase Inverter

016 IEEE Applied Power Electronics Conference and Exposition (APEC 2016), March 20-24, 2016, Long Beach, California, USADC-link capacitors in power electronic converters are a major constraint on improvement of power density as well as reliability. Evaluation of the dc-link capacitors in terms of power loss, ageing, and failure rate will play an important role in design stages of the next-generation power converters. This paper proposes a new evaluation circuit for dc-link capacitors used in a high-power three-phase inverter, which is intended for testing power loss, failure rate, ageing, and so on. The evaluation circuit produces a practical ripple current waveform and a dc bias voltage into a capacitor under test, in which the ripple current is equivalent to that generated by the three-phase inverter on the dc link. The evaluation circuit employs a full-scale current-rating and downscaled voltage-rating inverter for producing the ripple current, so that the power rating of the evaluation circuit is much smaller than that of a full-scale current rating and full-scale voltage rating inverter

Calorimetric Power-Loss Measurement of a High-Power Film Capacitor with Actual Ripple Current Generated by a PWM Inverter

This paper proposes a calorimetric power-loss measurement method suitable for a high-power film capacitor used in the dc link of a high-power three-phase PWM inverter. The measurement method is characterized by using a thermally-insulated container and an evaluation circuit for dc-link capacitors. Introduction of the thermally-insulated container achieves an accurate power loss measurement that is of the order of 1 W. The evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to those of the high-power three-phase PWM inverter although its power rating is 1/24 of the high-power inverter. This combination makes it possible to measure the power loss of the capacitor under actual voltage/current condition at low cost. Experimental results obtained from a 1200-V 210-kVA system verify the viability and effectiveness of the proposed method.The Tenth Annual IEEE Energy Conversion Congress and Exposition (ECCE 2018), September 23–27, 2018, Portland, Oregon, USA

60 GHz Wireless Signal Transmitting Gate Driver for IGBT

This paper shows the very first demonstration result of wireless IGBT gate drive using with 60 GHz wireless module with sufficient “real-time” control with 100 ns-level time delay with small fluctuation of the delay.2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC\u27s (ISPSD 2015), May 10-14, 2015, Hong Kong, Chin

A Case of Cochlear Implantation in a Patient with Superficial Siderosis

Superficial siderosis is a disease in which iron from hemoglobin is deposited in the central nervous system, resulting in conditions such as progressive sensorineural hearing loss, cerebellar ataxia, dementia, and pyramidal signs. A 30-year-old man with superficial siderosis received a cochlear implant in the left ear, which had shown complete hearing loss. Good auditory responses were obtained at 14 days after implantation. The postoperative average hearing level with the cochlear implant was 56.7 dB at 3 months and 55.0 dB at 6 months. However, the patient showed gradual hearing loss, and the dynamic range changed each time the electrode parameters were adjusted. To assess residual hearing ability, single-photon emission computed tomography was performed together with an assessment of electrical auditory brainstem response, which showed a good response and increased blood flow in both the temporal lobes. Based on this result, we asked the patient to continue using the cochlear implant to see whether a perception of speech response would be obtained. However, the patient discontinued using the cochlear implant because he could not hear satisfactorily. Hearing outcomes after cochlear implant surgery for patients with superficial siderosis are not necessarily good. Therefore, the possibility of unsatisfactory Results should be fully explained before recommending this surgery to patients

Selective loss of Purkinje cells in a patient with anti-gliadin-antibody-positive autoimmune cerebellar ataxia

The patient was an 84-year-old woman who had the onset of truncal ataxia at age 77 and a history of Basedow's disease. Her ataxic gait gradually deteriorated. She could not walk without support at age 81 and she was admitted to our hospital at age 83. Gaze-evoked nystagmus and dysarthria were observed. Mild ataxia was observed in all limbs. Her deep tendon reflex and sense of position were normal. IgA anti-gliadin antibody, IgG anti-gliadin antibody, anti-SS-A/Ro antibody, anti-SS-B/La antibody and anti-TPO antibody were positive. A conventional brain MRI did not show obvious cerebellar atrophy. However, MRI voxel based morphometry (VBM) and SPECT-eZIS revealed cortical cerebellar atrophy and reduced cerebellar blood flow. IVIg treatment was performed and was moderately effective. After her death at age 85, the patient was autopsied. Neuropathological findings were as follows: selective loss of Purkinje cells; no apparent degenerative change in the efferent pathways, such as the dentate nuclei or vestibular nuclei; no prominent inflammatory reaction. From these findings, we diagnosed this case as autoimmune cerebellar atrophy associated with gluten ataxia. All 3 autopsies previously reported on gluten ataxia have noted infiltration of inflammatory cells in the cerebellum