SECDA-TFLite: a toolkit for efficient development of FPGA-based DNN accelerators for edge inference

In this paper we propose SECDA-TFLite, a new open source toolkit for developing DNN hardware accelerators, integrated within the TFLite framework. The toolkit leverages the principles of SECDA, a hardware/software co-design methodology, to reduce the design time of optimized DNN inference accelerators on edge devices with FPGAs. With SECDA-TFLite, we reduce the initial setup costs associated with integrating a new accelerator design within a target DNN framework, allowing developers to focus on the design. SECDA-TFLite also includes modules for cost-effective SystemC simulation, profiling, and AXI-based data communication. As a case study, we use SECDA-TFLite to develop and evaluate three accelerator designs across seven common CNN models and two BERT-based models against an ARM A9 CPU-only baseline, achieving an average performance speedup across models of up to 3.4× for the CNN models and of up to 2.5× for the BERT-based models. Our code is available at https://github.com/gicLAB/SECDA-TFLite

AXI4MLIR: User-Driven automatic host code generation for custom AXI-Based accelerators

This document is a PrePrint . You can find it also in arXiv.org, with DOI: https://doi.org/10.48550/arXiv.2312.14821This paper addresses the need for automatic and efficient generation of host driver code for arbitrary custom AXI-based accelerators targeting linear algebra algorithms, an important workload in various applications, including machine learning and scientific computing. While existing tools have focused on automating accelerator prototyping, little attention has been paid to the host-accelerator interaction. This paper introduces AXI4MLIR, an extension of the MLIR compiler framework designed to facilitate the automated generation of host-accelerator driver code. With new MLIR attributes and transformations, AXI4MLIR empowers users to specify accelerator features (including their instructions) and communication patterns and exploit the host memory hierarchy. We demonstrate AXI4MLIR's versatility across different types of accelerators and problems, showcasing significant CPU cache reference reductions (up to 56%) and up to a 1.65x speedup compared to manually optimized driver code implementations. AXI4MLIR implementation is open-source and available at: t: https://github.com/AXI4MLIR/axi4mli

Optimal pharmacotherapy pathway in adults with diabetic peripheral neuropathic pain: the OPTION-DM RCT

Background: The mainstay of treatment for diabetic peripheral neuropathic pain is pharmacotherapy, but the current National Institute for Health and Care Excellence guideline is not based on robust evidence, as the treatments and their combinations have not been directly compared. Objectives: To determine the most clinically beneficial, cost-effective and tolerated treatment pathway for diabetic peripheral neuropathic pain. Design: A randomised crossover trial with health economic analysis. Setting: Twenty-one secondary care centres in the UK. Participants: Adults with diabetic peripheral neuropathic pain with a 7-day average self-rated pain score of ≥ 4 points (Numeric Rating Scale 0–10). Interventions: Participants were randomised to three commonly used treatment pathways: (1) amitriptyline supplemented with pregabalin, (2) duloxetine supplemented with pregabalin and (3) pregabalin supplemented with amitriptyline. Participants and research teams were blinded to treatment allocation, using overencapsulated capsules and matching placebos. Site pharmacists were unblinded. Outcomes: The primary outcome was the difference in 7-day average 24-hour Numeric Rating Scale score between pathways, measured during the final week of each pathway. Secondary end points included 7-day average daily Numeric Rating Scale pain score at week 6 between monotherapies, quality of life (Short Form questionnaire-36 items), Hospital Anxiety and Depression Scale score, the proportion of patients achieving 30% and 50% pain reduction, Brief Pain Inventory – Modified Short Form items scores, Insomnia Severity Index score, Neuropathic Pain Symptom Inventory score, tolerability (scale 0–10), Patient Global Impression of Change score at week 16 and patients’ preferred treatment pathway at week 50. Adverse events and serious adverse events were recorded. A withintrial cost–utility analysis was carried out to compare treatment pathways using incremental costs per quality-adjusted life-years from an NHS and social care perspective. Results: A total of 140 participants were randomised from 13 UK centres, 130 of whom were included in the analyses. Pain score at week 16 was similar between the arms, with a mean difference of –0.1 points (98.3% confidence interval –0.5 to 0.3 points) for duloxetine supplemented with pregabalin compared with amitriptyline supplemented with pregabalin, a mean difference of –0.1 points (98.3% confidence interval –0.5 to 0.3 points) for pregabalin supplemented with amitriptyline compared with amitriptyline supplemented with pregabalin and a mean difference of 0.0 points (98.3% confidence interval –0.4 to 0.4 points) for pregabalin supplemented with amitriptyline compared with duloxetine supplemented with pregabalin. Results for tolerability, discontinuation and quality of life were similar. The adverse events were predictable for each drug. Combination therapy (weeks 6–16) was associated with a further reduction in Numeric Rating Scale pain score (mean 1.0 points, 98.3% confidence interval 0.6 to 1.3 points) compared with those who remained on monotherapy (mean 0.2 points, 98.3% confidence interval –0.1 to 0.5 points). The pregabalin supplemented with amitriptyline pathway had the fewest monotherapy discontinuations due to treatment-emergent adverse events and was most commonly preferred (most commonly preferred by participants: amitriptyline supplemented with pregabalin, 24%; duloxetine supplemented with pregabalin, 33%; pregabalin supplemented with amitriptyline, 43%; p = 0.26). No single pathway was superior in cost-effectiveness. The incremental gains in quality-adjusted life-years were small for each pathway comparison [amitriptyline supplemented with pregabalin compared with duloxetine supplemented with pregabalin –0.002 (95% confidence interval –0.011 to 0.007) quality-adjusted life-years, amitriptyline supplemented with pregabalin compared with pregabalin supplemented with amitriptyline –0.006 (95% confidence interval –0.002 to 0.014) qualityadjusted life-years and duloxetine supplemented with pregabalin compared with pregabalin supplemented with amitriptyline 0.007 (95% confidence interval 0.0002 to 0.015) quality-adjusted life-years] and incremental costs over 16 weeks were similar [amitriptyline supplemented with pregabalin compared with duloxetine supplemented with pregabalin −£113 (95% confidence interval −£381 to £90), ABSTRACT NIHR Journals Library www.journalslibrary.nihr.ac.uk viii amitriptyline supplemented with pregabalin compared with pregabalin supplemented with amitriptyline £155 (95% confidence interval −£37 to £625) and duloxetine supplemented with pregabalin compared with pregabalin supplemented with amitriptyline £141 (95% confidence interval −£13 to £398)]. Limitations: Although there was no placebo arm, there is strong evidence for the use of each study medication from randomised placebo-controlled trials. The addition of a placebo arm would have increased the duration of this already long and demanding trial and it was not felt to be ethically justifiable. Future work: Future research should explore (1) variations in diabetic peripheral neuropathic pain management at the practice level, (2) how OPTION-DM (Optimal Pathway for TreatIng neurOpathic paiN in Diabetes Mellitus) trial findings can be best implemented, (3) why some patients respond to a particular drug and others do not and (4) what options there are for further treatments for those patients on combination treatment with inadequate pain relief. Conclusions: The three treatment pathways appear to give comparable patient outcomes at similar costs, suggesting that the optimal treatment may depend on patients’ preference in terms of side effects. Trial registration: The trial is registered as ISRCTN17545443 and EudraCT 2016-003146-89. Funding: This project was funded by the National Institute for Health and Care Research (NIHR) Health Technology Assessment programme, and will be published in full in Health Technology Assessment; Vol. 26, No. 39. See the NIHR Journals Library website for further project information

judeharis/axi_mlir: CGO 2024 Artifact v1.1

<p>This release contains code and instructions for the artifact evaluation for CGO 2024. Additionally we provide the bitmaps and hardware description files of the accelerators used within the paper, targeted for the PYNQ-Z1/Z2 board.</p&gt

judeharis/axi_mlir: CGO 2024 Artifact v1.0

<p>This release contains code and instructions for the artifact evaluation for CGO 2024. Additionally we provide the bitmaps and hardware description files of the accelerators used within the paper, targeted for the PYNQ-Z1/Z2 board.</p&gt

judeharis/axi_mlir: CGO 2024 Artifact v1.2

<p>This release contains code and instructions for the artifact evaluation for CGO 2024. Additionally we provide the bitmaps and hardware description files of the accelerators used within the paper, targeted for the PYNQ-Z1/Z2 board.</p&gt

Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs

Deep Neural Networks (DNNs) provide excellent performance in the field of machine learning and with the current trend of technology moving towards more mobile and decentralised processing of data, many industries face the challenge of performing DNN inference in constrained edge devices. Field Programmable Gate Arrays (FPGAs) are reconfigurable semiconductor circuits that are well suited for processing DNNs efficiently through hardware acceleration, as developers can adapt and redesign specialized DNN accelerators for new emergent DNNmodels. In this work, we design and implement hardware accelerators within the PYNQ Z1 board. Our designs outperform the CPU only inference of MobileNetV1 by 40% for single thread and 25.4% for dual thread

Hardware/Software Co-Design of Edge DNN Accelerators with TFLite

In this work we discuss SECDA-TFLite, a open-source toolkit for developing DNN hardware accelerators, integrated within the TFLite DNN inference framework. The toolkit leverages the principles of SECDA, a hardware/software co-design methodology which reduces the design time of optimized DNN inference accelerators on edge devices with FPGAs. Utilizing SECDA-TFLite, we further reduce the initial setup costs associated with integrating a new accelerator design within a target DNN framework, allowing developers to focus on the design. SECDA-TFLite also includes modules for cost-effective SystemC simulation, profiling, and AXI-based data communication. Additionally, we briefly cover our case study, where we use SECDA-TFLite to efficiently develop three different DNN accelerator designs on a PYNQ-Z1 board. We evaluate the three accelerator designs across five common CNN models and two BERT-based models, achieving an average performance speedup across models of up to 2.9x for the CNN models and an average speedup of up to 2.5x for the BERT-based models

SECDA: Efficient Hardware/Software Co-design of FPGA-based DNN Accelerators for Edge Inference

Edge computing devices inherently face tight resource constraints, which is especially apparent when deploying Deep Neural Networks (DNN) with high memory and compute demands. FPGAs are commonly available in edge devices. Since these reconfigurable circuits can achieve higher throughput and lower power consumption than general purpose processors, they are especially well-suited for DNN acceleration. However, existing solutions for designing FPGA-based DNN accelerators for edge devices come with high development overheads, given the cost of repeated FPGA synthesis passes, reimplementation in a Hardware Description Language (HDL) of the simulated design, and accelerator system integration. In this paper we propose SECDA, a new hardware/software co-design methodology to reduce design time of optimized DNN inference accelerators on edge devices with FPGAs. SECDA combines cost-effective SystemC simulation with hardware execution, streamlining design space exploration and the development process via reduced design evaluation time. As a case study, we use SECDA to efficiently develop two different DNN accelerator designs on a PYNQ-Z1 board, a platform that includes an edge FPGA. We quickly and iteratively explore the system’s hardware/software stack, while identifying and mitigating performance bottlenecks. We evaluate the two accelerator designs with four common DNN models, achieving an average performance speedup across models of up to 3.5× with a 2.9× reduction in energy consumption over CPU-only inference