Effect of an oxide cap layer and fluorine implantation on the metal-induced lateral crystallization of amorphous silicon

In this work, we investigate the effect of oxide cap layer on the metal-induced lateral crystallization (MILC) of amorphous silicon. The MILC is characterized at temperatures in the range 550 to 428°C using Nomarski optical microscopy and Raman spectroscopy. It is shown that better lateral crystallization is obtained when the oxide cap layer is omitted, with the crystallization length increasing by 33% for a 15 hour anneal at 550°C. A smaller increase of about 10% is seen at lower temperatures between 525°C and 475°C and no increase is seen below 450°C. It is also shown that the detrimental effect of the oxide cap layer can be dramatically reduced by giving samples a fluorine implant prior to the MILC anneal. Raman spectroscopy shows that random grain growth is significantly less for unimplanted samples without an oxide cap and also for fluorine implanted samples both with and without an oxide cap. The crystallization length improvement for samples without an oxide cap layer is explained by the elimination of random grain crystallization at the interface between the amorphous silicon and the oxide cap layer

A new vertical power MOSFET with extremely reduced on resistance and high switching speed with multilayer structure

A vertical power MOSFET’s whose n-drift region is stacked by alternate pn structure named as MULTILAYER POWER MOSFET has been proposed for high voltage application with extremely low on-resistance. However, the device capacitance increases by a significant amount that has the possibility to reduce the switching speed of the devices. Therefore, a trade off is established to reduce RC time constant by changing the thickness of the stacking. The electrical characteristics of a CONVENTIONAL POWER MOSFET having trench contact for the source and body regions are compared with that of our proposed multilayer structure. The device proves itself as a high performance MOSFET with high speed and high storage capacity

Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics

Gate capacitance of metal-oxide-semiconductor devices with ultra-thin high-K gate-dielectric materials is calculated taking into account the penetration of wave functions into the gate-dielectric. When penetration effects are neglected, the gate capacitance is independent of the dielectric material for a given equivalent oxide thickness (EOT). Our selfconsistent numerical results show that in the presence of wave function penetration, even for the same EOT, gate capacitance depends on the gate-dielectric material. Calculated gate capacitance is higher for materials with lower conduction band offsets with silicon. We have investigated the effects of substrate doping density on the relative error in gate capacitance due to neglecting wave function penetration. It is found that the error decreases with increasing doping density. We also show that accurate calculation of the gate capacitance including wave function penetration is not critically dependent on the value of the electron effective mass in the gate-dielectric region

Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from ?50 to 200?C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain–body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical (110) pillar sidewalls and the horizontal (100) wafer surface

Improved drive current in RF vertical MOSFETS using hydrogen anneal

This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800 ?C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors without the hydrogen anneal. The value of drive current achieved is 250 ?A/?m, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H2 anneal is also shown to decrease the OFF-state leakage current by a factor of three

Increased lateral crystallization width during nickel induced lateral crystallization of amorphous silicon using fluorine implantation

This paper reports a study of the effect of fluorine implantation on the nickel-induced lateral crystallization of amorphous silicon. To distinguish the effects of the fluorine and the implantation damage, the fluorine implant is either made directly into the a-Si or into the buffer oxide below the a-Si. For a 20 h anneal at 500°C, both types of fluorine implant give a 65% increase in the lateral crystallization width, a five times reduction in the density of nickel silicide precipitates, and an improved grain texture. In contrast, for 20 h anneals at 550 and 600°C, both types of fluorine implant give 29% and 85% reductions in the lateral crystallization width, respectively. The identical results obtained for fluorine implantation into the a-Si and the buffer oxide indicates that the effects observed are due to chemical effects of the fluorine rather than implantation damage in the a-Si. The increased crystallization width at 500°C is explained by the suppression of random crystallization at the bottom a-Si/SiO2 interface. The reduced crystallization widths at 550 and 600°C are attributed to the diffusion and activation of fluorine and the formation of Si–F bonds making the a-Si more resistant to silicide-mediated phase transformation