An embedded system supporting dynamic partial reconfiguration of hardware resources for morphological image processing

Processors for high-performance computing applications are generally designed with a focus on high clock rates, parallelism of operations and high communication bandwidth, often at the expense of large power consumption. However, the emphasis of many embedded systems and untethered devices is on minimal hardware requirements and reduced power consumption. With the incessant growth of computational needs for embedded applications, which contradict chip power and area needs, the burden is put on the hardware designers to come up with designs that optimize power and area requirements. This thesis investigates the efficient design of an embedded system for morphological image processing applications on Xilinx FPGAs (Field Programmable Gate Array) by optimizing both area and power usage while delivering high performance. The design leverages a unique capability of FPGAs called dynamic partial reconfiguration (DPR) which allows changing the hardware configuration of silicon pieces at runtime. DPR allows regions of the FPGA to be reprogrammed with new functionality while applications are still running in the remainder of the device. The main aim of this thesis is to design an embedded system for morphological image processing by accounting for real time and area constraints as compared to a statically configured FPGA. IP (Intellectual Property) cores are synthesized for both static and dynamic time. DPR enables instantiation of more hardware logic over a period of time on an existing device by time-multiplexing the hardware realization of functions. A comparison of power consumption is presented for the statically and dynamically reconfigured designs. Finally, a performance comparison is included for the implementation of the respective algorithms on a hardwired ARM processor as well as on another general-purpose processor. The results prove the viability of DPR for morphological image processing applications

Design and Implementation of ZCS BUCK Converter

Buck converters are step-down DC-DC converters that are widely being used in different electronic devices like laptops,PDA’s,cell phones and also electric vehicles to obtain different level of voltages. These converters are nothing but ,high frequency switching devices operating on PWM principle. The need for more and more lighter and smaller electronic devices propels the need for reduced size of converters operating at higher load currents. With all these inadvertent conditions the switching frequency has jumped from KHz range to MHz range.The switching devices are made to turn on and turn off the entire load current at high di/dt , and also withstand high voltage stress across them.Due to these two effects there occurs increased power losses in these converters and reduces the efficiency significantly. The reduction in efficiency is highly unacceptable as it leads to shorter battery life and derated device conditions. The shortcomings explained above can be minimised and upto some extent eliminated if each switch is made to turn-on and turn-off when the voltage across it and/or current through it is zero at the instant of switching. The converter circuits which employ zero voltage and /or zero current switching are known as Resonant converters. In most of these converters some form of L-C resonance is used, that is why these are known as resonant converters. In this project a detailed study of zero current switching buck converters is done and also practically implemented in hardware. In addition a mathematical analysis of switching loss occuring in MOSFET’s is also presented and a short study of zero voltage switching is also appended. During the hardware implementation the Ton,Toff and operating frequency were found out and thoroughly tuned through the IC555 circuit and various waveforms across inductors,capacitors,load resistor and test points were noted down. These waveforms were found to be in precise proximity of the theoretically observed waveforms

Fast Proxy Re-Encryption for Publish/Subscribe Systems

We develop two IND-CPA-secure multi-hop unidirectional Proxy Re-Encryption (PRE) schemes by applying the Ring-LWE (RLWE) key switching approach from the homomorphic encryption literature. Unidirectional PRE is ideal for secure publish-subscribe operations where a publisher encrypts information using a public key without knowing upfront who the subscriber will be and what private key will be used for decryption. The proposed PRE schemes provide a multi-hop capability, meaning that when PRE-encrypted information is published onto a PRE-enabled server, the server can either delegate access to specific clients or enable other servers the right to delegate access. Our first scheme (which we call NTRU-ABD-PRE) is based on a variant of the NTRU-RLWE homomorphic encryption scheme. Our second and main PRE scheme (which we call BV-PRE) is built on top of the Brakerski-Vaikuntanathan (BV) homomorphic encryption scheme and relies solely on the RLWE assumption. We present an open-source C++ implementation of both schemes and discuss several algorithmic and software optimizations. We examine parameter selection tradeoffs in the context of security, runtime/latency, throughput, ciphertext expansion, memory usage, and multi-hop capabilities. Our experimental analysis demonstrates that BV-PRE outperforms NTRU-ABD-PRE both in single-hop and multi-hop settings. The BV-PRE scheme has a lower time and space complexity than existing IND-CPA-secure lattice-based PRE schemes, and requires small concrete parameters, making the scheme computationally efficient for use on low-resource embedded systems while still providing 100 bits of security. We present practical recommendations for applying the PRE schemes to several use cases of ad-hoc information sharing for publish-subscribe operations

Fast Proxy Re-Encryption for Publish/Subscribe Systems

© 2017 ACM. We develop two IND-CPA-secure multihop unidirectional Proxy Re-Encryption (PRE) schemes by applying the Ring-LWE (RLWE) key switching approach from the homomorphic encryption literature. Unidirectional PRE is ideal for secure publish-subscribe operations where a publisher encrypts information using a public key without knowing upfront who the subscriber will be and what private key will be used for decryption. The proposed PRE schemes provide a multihop capability, meaning that when PRE-encrypted information is published onto a PRE-enabled server, the server can either delegate access to specific clients or enable other servers the right to delegate access. Our first scheme (which we call NTRU-ABD-PRE) is based on a variant of the NTRU-RLWE homomorphic encryption scheme. Our second and main PRE scheme (which we call BV-PRE) is built on top of the Brakerski-Vaikuntanathan (BV) homomorphic encryption scheme and relies solely on the RLWE assumption. We present an open-source C++ implementation of both schemes and discuss several algorithmic and software optimizations. We examine parameter selection tradeoffs in the context of security, runtime/latency, throughput, ciphertext expansion, memory usage, and multihop capabilities. Our experimental analysis demonstrates that BV-PRE outperforms NTRU-ABD-PRE in both single-hop and multihop settings. The BVPRE scheme has a lower time and space complexity than existing IND-CPA-secure lattice-based PRE schemes and requires small concrete parameters, making the scheme computationally efficient for use on low-resource embedded systems while still providing 100 bits of security. We present practical recommendations for applying the PRE schemes to several use cases of ad hoc information sharing for publish-subscribe operations

Effect of Different Physical and Chemical Treatments on Germination and Seedling Establishment in Spine gourd (Momordica dioica Roxb.)

The experiment was conducted at Department of Vegetable Science, OUAT, Bhubaneswar from 2019-2021. Stored spine gourd seeds of six months old were used in this experiment. The seeds were first given various physical treatments (T1: control, T2: 48 hours soaking in  water, T3: hot water treatment for 20 minutes + 48 hours soaking in water, T4: scarification by sand paper + 48 hours soaking in water, T5: removal of seed coat + 48 hours soaking in water) followed by chemical treatments (C1: GA3 100 ppm, C2: GA3 200 ppm, C3: KNO3 1%, C4: KNO3 2%, C5: Thiourea 1%,  C6: Thiourea 2% & C7: control). The experiment was laid out in factorial CRD design with 35 treatment combinations replicated twice. The seeds were sown in plastic trays containing coco peat media. The effect of these treatments on number of days taken for initial germination, length of shoot, root, number of roots per seedling and percentage of seedling establishment in main field were recorded. From the data recorded, it was observed that among the physical treatments, T5 (removal of seed coat + 48 hours soaking in water), among the chemical treatments, C1 (GA3 100 ppm) and between the interactions, T5C1 (removal of seed coat + 48 hours soaking in water + GA3 100 ppm) took minimum number of days for initial germination with highest shoot and root length, maximum number of roots per seedling and highest establishment percentage in field. The lowest values were recorded in case of control. So, it can be concluded that removal of seed coat followed by 48 hour soaking in water and GA3 100 ppm treatment resulted early germination with desirable seedling traits and highest establishment percent in main field