MTCA.4 - modular measurement and control system with sub-nanosecond time synchronization and support for RF applications

Abstract—The Micro TCA platform is rapidly developing modular technology for measurement and control systems. There are available versions for laboratories, military and aviation. The newest release of the standard (MTCA.4) supports high frequency RF applications like particle accelerators, radio, telecom and radar. The PERG group together with partners from Europe and Poland takes active part in development process, i.e. implementation of sub-ns synchronization, event and RF distribution system over fibre networks. It enhances significantly capabilities of MTCA platform in distributed measurement systems (i.e. passive radars) and enables fully deterministic operation of hard realtime control systems

The control system of the AEgIS experiment at CERN

The AEgIS experiment at CERN recently decided to adopt a control system solution based on the Sinara/ARTIQ open hardware and software infrastructure. This decision meant to depart from the previously used paradigm of custom-made electronics and software to control the experiment's equipment. Instead, adopting a solution with long-term support and used in many quantum physics experiments guarantees a vivid community using similar infrastructures. This transition reduces the risks and development timeline for integrating new equipment seamlessly within the setup. This work reviews the motivation, the setup, and the chosen hardware and presents several planned further steps in developing the control system

Feasibility of FPGA to HPC computation migration of plasma impurities diagnostic algorithms

We present a feasibility study of fast events parameters estimation algorithms regarding their execution time. It is the first stage of procedure used on data gathered from gas electron multiplier (GEM) detector for diagnostic of plasma impurities. Measured execution times are estimates of achievable times for future and more complex algorithms. The work covers usage of Intel Xeon and Intel Xeon Phi - high-performance computing (HPC) devices as a possible replacement for FPGA with highlighted advantages and disadvantages. Results show that less than 10 ms feedback loop can be obtained with the usage of 25% hardware resources in Intel Xeon or 10% resources in Intel Xeon Phi which leaves space for future increase of algorithms complexity. Moreover, this work contains a simplified overview of basic problems in actual measurement systems for diagnostic of plasma impurities, and emerging trends in developed solutions

Urukul – open-source frequency synthesizer module for quantum physics

We describe Urukul, a frequency synthesizer based on direct digital synthesis (DDS), optimized for wave generate control in atomic, molecular and optical (AMO) physics experiments. The Urukul module is a part of the Sinara family of modular, open-source hardware designed for the ARTIQ quantum operating system. The Urukul has 4-channel, sub-Hz frequency resolution, controlled phase steps and accurate output amplitude control. The module is available in two population variants. This paper presents Urukul module construction and obtained characteristic

Sampler – open-source data acquisition module for quantum physics

The Sinara hardware platform is a modular, open-source measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and sub-microsecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics

Sampler – open-source data acquisition module for quantum physics

The Sinara hardware platform is a modular, open-source measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and sub-microsecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics

Zero-Suppression Trigger Mode for GEM detector measurement system

A novel approach to a trigger mode in the GasElectron Multiplier (GEM) detector readout system is presented.The system is already installed at WEST tokamak. The articlebriefly describes the architecture of the GEM detector and themeasurement system. Currently the system can work in twotrigger modes: Global Trigger and Local Trigger. All trigger processingblocks are parts of the Charge Signal Sequencer modulewhich is responsible for transferring data to the PC. Therefore,the article presents structure of the Sequencer with details aboutbasic blocks, theirs functionality and output data configuration.The Sequencer with the trigger algorithms is implemented inan FPGA chip from Xilinx. Global Trigger, which is a defaultmode for the system, is not efficient and has limitations due tostoring much data without any information. Local trigger whichis under tests, removes data redundancy and is constructed tosend only valid data, but the rest of the software, especially on thePC side, is still under development. Therefore authors proposethe trigger mode which combines functionality of two existingmodes. The proposed trigger, called Zero Suppression Trigger, iscompatible with the existing interfaces of the PC software, butis also capable to verify and filter incoming signals and transferonly recognized events. The results of the implementation andsimulation are presented

Zero-Suppression Trigger Mode for GEM detector measurement system

A novel approach to a trigger mode in the GasElectron Multiplier (GEM) detector readout system is presented.The system is already installed at WEST tokamak. The articlebriefly describes the architecture of the GEM detector and themeasurement system. Currently the system can work in twotrigger modes: Global Trigger and Local Trigger. All trigger processingblocks are parts of the Charge Signal Sequencer modulewhich is responsible for transferring data to the PC. Therefore,the article presents structure of the Sequencer with details aboutbasic blocks, theirs functionality and output data configuration.The Sequencer with the trigger algorithms is implemented inan FPGA chip from Xilinx. Global Trigger, which is a defaultmode for the system, is not efficient and has limitations due tostoring much data without any information. Local trigger whichis under tests, removes data redundancy and is constructed tosend only valid data, but the rest of the software, especially on thePC side, is still under development. Therefore authors proposethe trigger mode which combines functionality of two existingmodes. The proposed trigger, called Zero Suppression Trigger, iscompatible with the existing interfaces of the PC software, butis also capable to verify and filter incoming signals and transferonly recognized events. The results of the implementation andsimulation are presented

Soft X-ray diagnostic system upgrades and data quality monitoring features for tokamak usage

The validation of the measurements quality after on-site diagnostic system installation is necessary in order to provide reliable data and output results. This topic is often neglected or not discussed in detail regarding measurement systems. In the paper recently installed system for soft X-ray measurements is described in introduction. The system is based on multichannel GEM detector and the data is collected and sent in special format to PC unit for further postprocessing. The unique feature of the system is the ability to compute final data based on raw data only. The raw data is selected upon algorithms by FPGA units. The FPGAs are connected to the analog front-end of the system and able to register all of the signals and collect the useful data. The interface used for data streaming is PCIe Gen2 x4 for each FPGA, therefore high throughput of the system is ensured. The paper then discusses the properties of the installation environment of the system and basic functionality mode. New features are described, both in theoretical and practical approach. New modes correspond to the data quality monitoring features implemented for the system, that provide extra information to the postprocessing stage and final algorithms. In the article is described also additional mode to perform hardware simulation of signals in a tokamak-like environment using FPGAs. The summary describes the implemented features of the data quality monitoring features and additional modes of the system