19 research outputs found

    Dreidimensionaler Nanostrukturkörper und Verfahren zum Herstellen eines dreidimensionalen Nanostrukturkörpers

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    Die Erfindung betrifft einen dreidimensionalen Nanostrukturkörper (200) sowie ein Verfahren zum Erzeugen eines dreidimensionalen Nanostrukturkörpers (200). Das Verfahren beinhaltet unter anderem ein Bereitstellen eines Substrats (203) mit einem Opferschichtstapel (205), wobei der Opferschichtstapel (205) mindestens eine erste und eine zweite Opferschicht (205a, 205b) aufweist, und wobei der Opferschichtstapel (205) mindestens eine Öffnung (207) aufweist, die sich durch den Opferschichtstapel (205) hindurch bis zu dem Substrat (203) erstreckt. Ferner umfasst das Verfahren ein Anordnen einer ersten Materialschicht (201m) an zumindest einer Seitenwand (208) der Öffnung (207), und ein Anordnen einer zweiten Materialschicht (202m) auf der sich innerhalb der Öffnung (207) befindlichen ersten Materialschicht (201m). Erfindungsgemäß beinhaltet das Verfahren ein Entfernen der ersten Opferschicht (205a) und Entfernen von Teilen der ersten Materialschicht (201 m), die zuvor von der ersten Opferschicht (205a) bedeckt waren, unter Beibehaltung der zweiten Materialschicht (202m), und ein Entfernen der zweiten Opferschicht (205b) unter Beibehaltung der ersten und der zweiten Materialschicht (201m, 202m)

    Fabrication and electrochemical characterization of ruthenium nanoelectrodes

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    The Fraunhofer IMS has recently developed a technique for producing nanoelectrodes that are generated by atomic layer deposition (ALD) in a via deep reactive ion etching (DRIE) structured sacrificial layer. This method enables the fabrication of CMOS- and biocompatible nanoelectrodes with suitable ALD-materials. Improvements of the established fabrication processes and the electrochemical characterization of such electrodes are presented. In the frame of the Fraunhofer-Max-Planck cooperation project ZellMOS different types of nanoelectrodes are studied. Their diameter is in the range of 200 nm and thereby sufficiently small to be taken up by living cells. In addition, the electrodes are mechanically enforced by an oxide layer at the nanoelectrodes’ bottom

    Fabrication and electrochemical characterization of ruthenium nanoelectrodes

    No full text
    The Fraunhofer IMS has recently developed a technique for producing nanoelectrodes that are generated by atomic layer deposition (ALD) in a via deep reactive ion etching (DRIE) structured sacrificial layer. This method enables the fabrication of CMOS- and biocompatible nanoelectrodes with suitable ALD-materials. Improvements of the established fabrication processes and the electrochemical characterization of such electrodes are presented. In the frame of the Fraunhofer-Max-Planckcooperation project ZellMOS different types of nanoelectrodes are studied. Their diameter is in the range of 200 nm and thereby sufficiently small to be taken up by living cells. In addition, the electrodes are mechanically enforced by an oxide layer at the nanoelectrodes’ bottom

    CMOS kompatible, nanomodifizierte Multi-Elektroden-Arrays

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    The integration of carbon nanotubes (CNT) on a CMOS compatible multi-electrode-array (MEA) is presented. Within the project InMEAs, CNTs are deposited directly on a high-temperature-stable MEA platform. The Fraunhofer IMS has developed a 0.8 µm bulk-substrate CMOS-technology based on tungsten metallization, in this case the threshold voltage is shifted only slightly after a temperature step of 700 °C / 30 min. By using the mixed catalyst PtFe the Fraunhofer IKTS could reduce the process temperature for CNT deposition to 620 °C

    Tapering of nanoelectrodes for an intracellular contact via a double hard mask technique

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    To realize an intracellular contact between nanoelectrodes and cells, a sufficient small electrode diameter is needed [1]. A sacrificial layer process developed by the Fraunhofer IMS using deep reactive ion etching and atomic layer deposition [2] is varied. A double hard mask technique is used to taper structures in a sacrificial layer and thereby the nanoelectrodes’ diameter. The principles and evaluation of the spacing technique, which allows the fabrication of sublithographic structures, are presented here

    ALD-based 3D-capacitors for harsh environments

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    Passive components like capacitors for harsh environments become more and more important, e. g. in the field of deep drilling, aerospace or in the automotive industry. They have to withstand temperatures up to 300 °C with a good performance concerning leakage current, breakdown voltage and capacitance density. The whole process flow has to be CMOS-compatible in order to offer the possibility for CMOS-integration. A highly n-doped Sisubstrate (doping concentration about 1020 cm-3, phosphorus) acts as bottom electrode to keep the process flow as simple as possible. The capacitors are 3D-integrated to achieve a high capacitance density. For the dielectric layer and the upper electrode, atomic layer deposited (ALD) materials are used. The combination of the medium- and high-k dielectrics and the electrode materials are optimized, as well as some of the ALD processes, to reach an optimum in leakage current and breakdown voltage. At a bias voltage of 3 V at room temperature, the leakage current amounts about 5 pA/mm², at 300 °C about 40 pA/mm². Up to ± 15 V for room temperature, respectively up to ± 10 V for 300 °C, no soft-breakdown is observed, indicating the absence of significant Fowler-Nordheim tunneling

    Heterogene Integration einer Miniatur-Solarzelle für autarke Sensoren

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    In this contribution we present a silicon-based miniature solar cell that can be integrated heterogeneously onto a CMOS chip developed by Fraunhofer IMS. The solar cell is bonded onto the CMOS chip and serves as the electrical power supply of the sensor system. Furthermore the bonded solar cell can be used as a chip-scale-package for the sensor, thereby enabling a compact and cost-effective sensor node having minimal dimensions. The solar cell is manufactured using well-established methods of semiconductor process technology and bonded onto the CMOS chip using CMOS compatible methods
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