X86_64 vs Aarch64 Performance Validation with COTSon

In this study, we provide a set of architectural parameters for the HPLabs COTSon simulator that can be used to model existing processors, such as the Intel i7700 (X86_64 architecture) and the ARM A53 (Aarch64 architecture). We carry out an initial validation, by comparing the execution time while performing the weak scaling of the architecture, in the case of two common benchmarks. We use the Recursive Fibonacci and Matrix Multiplication benchmarks for simplicity. By using the simulator, we can then further study the sensitivity of the architecture and derive which features may matter most to evaluate the performance. Our goal here is to verify that the COTSon simulator can be used to model both the X86_64 and Aarch64 architectures. Based on this validation study, we have the possibility to analyze the bottlenecks and desirable microarchitectural features of modern architectures

Government failure, opposition success? Electoral performance in Portugal and Italy at the time of the crisis. Jean Monnet Occasional Paper 05/2014

The costs of the crisis in Southern European countries have not been only economic but political. Economic crises tend to lead to government instability and termination while political challengers are expected to exploit this contingent window of opportunity to gain an advantage over incumbents in national elections. The current crisis seems to make no exception, looking at the results of the general elections recently held in Southern Europe. However, this did not always lead to a clear victory of the main opposition parties. In most of the elections, in fact, the incumbent parties’ loss did not coincide with the official opposition’s gain. The extreme case is represented by Italy, where both the outgoing government coalition led by Silvio Berlusconi – setting aside for the moment the technocratic phase – and its main challenger, the centre left coalition, ended up losing millions of voters and a new political force, the Five Star Movement, obtained about 25 per cent of votes. On the opposite side there is Portugal. Only in Portugal did the vote increase for the centre right PSD, in fact, exceed the incumbent socialists’ loss. The present work aims at exploring the factors which might account for this significant divergence between the two cases

Reconfigurable Logic Interface Architecture for CPU-FPGA Accelerators

Programmable System-on-Chips (SoC) are a flexible solution to offload part of the computational power from CPU to FPGA and accelerate the execution time. In today ARM-based SoCs, CPU and FPGA are usually connected to each other through several different communication links based on AMBA standard. This paper presents two possible design as reconfigurable logic interface architectures to be employed as a high performance interface module in programmable logic accelerators. These designs provide us with programmability for bidirectional data communication paths between CPU memory-mapped master interface and FPGA. Our first proposed design offers up to 32 configurable registers while the other has up to 32 configurable FIFOs to be able to exchange larger data. Both of these architectures communicate to programmble logic accelerators through the data stream channels

From COTSon to HLS: translating timing into an architecture

Nowadays, the increasing core number benefits many workloads, but programming limitations to exploiting full performance still remain. A Data-Flow execution model is capable of taking advantage of the full parallelism offered by multicore systems. In such model, the execution can be decomposed in fine-grain threads named Data-Flow Threads (DF-Threads) so that each of them can execute only when their inputs are available. The execution overhead and power consumption is lowered thanks to the reduction of the data push-pull, as well as the burden of thread management

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise: Designing a Computer Architecture via HLS)

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours

Heritage and cultural accessibility: the role of design in the creation of an intercultural dialogue

The contribution intends to present a reflection in the field of design for the enhancement of cultural heritage in terms of cultural accessibility, and the implications related to the reception and integration of communities and social groups nowadays excluded. Within this context, design skills can be made available as tools to generate mediation processes between these cultural multiplicities, encouraging actions to enhance diversity and activating a dialogue between people and cultures. Design can devise strategies, services and integrated communication systems to facilitate meeting and exchange between the heritage and the multicultural community that lives in a territory. By mapping certain virtuous design actions (at different scales, such as graphic, product and strategic design), we aim to highlight new possible approaches in the design for the fruition of cultural heritage, according to which the design act presents itself as a “translation” of values and identities for new and existing communities that cohabit in a territory

Structured and unstructured activities and teenager crime. Data Analysis of ISRD-2

En este artículo se muestran los resultados de una investigación cuyo propósito ha sido comprender y determinar si existe una relación entre la delincuencia y diversas actividades estructuradas y no estructuradas, que forman parte de la vida de los jóvenes. Los datos que se procesaron en este estudio provienen de la segunda encuesta internacional de delincuencia autoinformada o International Self-Reported Delinquency Study (ISRD-2), realizada en Suiza con aproximadamente 3000 alumnos de entre 13 y 16 años. En este contexto, la investigación se ha centrado en las teorías de las oportunidades. El estudio ha estado orientado por la siguiente idea: el tiempo dedicado a la práctica de actividades estructuradas (como aquellas realizadas con los padres, realizar los deberes escolares, leer libros, leer revistas o cómics) reduce en los adolescentes el riesgo de cometer conductas delictivas, por el contrario, el hecho de participar en actividades no estructuradas (deambular de un lado a otro con los amigos ir a discotecas o a conciertos, salir de fiesta por la noche, chatear con desconocidos) aumenta la probabilidad de un comportamiento delictivo. Los resultados confirman las hipótesis que se habían formulado: las actividades estructuradas disminuyen la implicación en la delincuencia, y las actividades desestructuradas contrariamente representan un factor de riesgo. Por estas razones, debe considerarse la posibilidad de realizar investigaciones más específicas sobre la relación entre el ocio y la delincuencia. Es fundamental tener en cuenta una gama más amplia de actividades realizadas por los jóvenes, si se quiere relevar el peso de esta variable sobre el comportamiento de los adolescentes.Abstract: The purpose of this study is to understand and determine whether there is a relationship between crime and various structured and unstructured activities that are part teenager´s life. The collected data come from the second international survey of self-reported crime or Self-Reported Delinquency Study (ISRD-2), conducted in Switzerland with approximately 3,000 students between 13 and 16 years. In this context, research has been focused on theories of opportunities. It begins by considering that the time devoted to the practice of structured activities (activities with parents, doing homework, reading books, reading magazines or comics) reduces the risk of committing criminal acts, however, the act of participating in unstructured activities (hanging out with friends, going to clubs or concerts, partying at night, playing computer games or chatting with strangers) increases the likelihood of criminal behavior. The results confirm the hypothesis formulated: structured activities decreased involvement in crime, and unstructured activities contrary represent a risk factor. For these reasons, there must be more specific research carried out on the relationship between leisure and crime. It is essential to take into account a broader range of activities undertaken by young people to measure the weight of this variable on the behavior of adolescents in a closer loo

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours

Room temperature Bloch surface wave polaritons

Polaritons are hybrid light-matter quasi-particles that have gathered a significant attention for their capability to show room temperature and out-of-equilibrium Bose-Einstein condensation. More recently, a novel class of ultrafast optical devices have been realized by using flows of polariton fluids, such as switches, interferometers and logical gates. However, polariton lifetimes and propagation distance are strongly limited by photon losses and accessible in-plane momenta in usual microcavity samples. In this work, we show experimental evidence of the formation of room temperature propagating polariton states arising from the strong coupling between organic excitons and a Bloch surface wave. This result, which was only recently predicted, paves the way for the realization of polariton devices that could allow lossless propagation up to macroscopic distances