Variations in Plasma Membrane Topography Can Explain Heterogenous Diffusion Coefficients Obtained by Fluorescence Correlation Spectroscopy

Fluorescence correlation spectroscopy (FCS) is frequently used to study diffusion in cell membranes, primarily the plasma membrane. The diffusion coefficients reported in the plasma membrane of the same cell type and even within single cells typically display a large spread. We have investigated whether this spread can be explained by variations in membrane topography throughout the cell surface, that changes the amount of membrane in the FCS focal volume at different locations. Using FCS, we found that diffusion of the membrane dye DiI in the apical plasma membrane was consistently faster above the nucleus than above the cytoplasm. Using live cell scanning ion conductance microscopy (SICM) to obtain a topography map of the cell surface, we demonstrate that cell surface roughness is unevenly distributed with the plasma membrane above the nucleus being the smoothest, suggesting that the difference in diffusion observed in FCS is related to membrane topography. FCS modeled on simulated diffusion in cell surfaces obtained by SICM was consistent with the FCS data from live cells and demonstrated that topography variations can cause the appearance of anomalous diffusion in FCS measurements. Furthermore, we found that variations in the amount of the membrane marker DiD, a proxy for the membrane, but not the transmembrane protein TCRζ or the lipid-anchored protein Lck, in the FCS focal volume were related to variations in diffusion times at different positions in the plasma membrane. This relationship was seen at different positions both at the apical cell and basal cell sides. We conclude that it is crucial to consider variations in topography in the interpretation of FCS results from membranes.QC 20201013</p

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5× higher performance and 2.4× higher computational energy efficiency at a 1.6× larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.publishedVersionPeer reviewe

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system’s performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic,..), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a 0.18µm SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x.acceptedVersionPeer reviewe