Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL

The present work is an analysis of the performance of the basic vector operations AXPY, DOT and SpMV using OpenCL. The code was tested on the NVIDIA Tesla S2050 GPU and Intel Xeon Phi 3120A coprocessor. Due to the nature of the AXPY function, only two versions were implemented, the routine to be executed by the CPU and the kernel to be executed on the previously mentioned devices. It was studied how they perform for different vector’s sizes. Their results show the NVIDIA architecture better suited for the smaller vectors sizes and the Intel architecture for the larger vector’s sizes. For the DOT and SpMV functions, there are three versions implemented. The first is the CPU routine, the second one is an OpenCL kernel that uses local memory and the third one is an OpenCL kernel that only uses global memory. The kernels that use local memory are tested by varying the size of the work-group; the kernels that only uses global memory are tested by varying the arrays size. In the case of the first ones, the results show the optimum work-group size and that the NVIDIA architecture benefits from the use of local memory. For the latter kernels, the results show that larger computational loads benefits the Intel architectureThis work has been supported by FEDER funds and Xunta de Galicia under contract GRC 2014/008, and by Spanish Government (MCYT) under project TEC2010-17320 and TIN-2013-41129-PS

Spin-polarized transport in a full magnetic pn tunnel junction

Simulations of the tunneling current as a function of voltage and temperature for a Zener diode where both sides are ferromagnetic have been performed. The current is evaluated as a function of the applied bias, the magnetization, and the temperature on the diode. The tunneling magnetoresistance is also analyzed. Mn doped GaAs parameters were used to simulate a highly asymmetric doped diode, which leads to a large difference on the magnetization values between the p and n sidesThis work was supported by Spanish Government Grant Nos. TIN2007-67537-C03-01 and TEC2010-17320 and by Xunta de Galicia Grant Nos. DXIDI09TIC001CT and INCITE08PXIB206094PRS

Vertical-Tunnel-Junction (VTJ) Solar Cell for Ultra-High Light Concentrations (>2000 Suns)

A novel architecture of cell structure tailored to ultra-high (>2000 suns) concentration ratios is proposed. The basic solar cell consists of two p-n junctions connected in series by a highly doped tunnel diode with the metallic contacts located laterally. The tunneling connection allows using direct band-gap semiconductor compounds aiming to optimize the absorption of the spectrum. The performance of the novel architecture is investigated up to ultra-high concentration using TCAD software. Simulations show its viability for developing a new generation of solar cells to increase the potential in terms of efficiency and cost reduction of ultra-high concentrator systems. The solar cell does not show any degradation with concentration and efficiency as high as 28.4% at 15000 suns has been obtained for a preliminary designThe work of E. F. Fernández and F. Almonacid was supported by the Spanish Economy Ministry and FEDER funds under Project ENE2016-78251-R. The work of N. Seoane and A. J. García-Loureiro was supported in part by the Spanish Ministry of Economy and Competitiveness and FEDER funds under Grants TEC2014-59402-JIN and TIN2016-76373-P and in part by the Xunta de Galicia and FEDER funds under Grant GRC 2014/008S

Vacuum annealing effect on physical properties and electrical circuit model of ZnO:Sn/SnO2:F bilayer structure

Tin doped Zinc oxide/Fluorine doped tin dioxide bilayer films (ZnO:Sn/SnO2:F) were deposited on glass substrates using spray pyrolysis technique. The effect of vacuum annealing at different temperatures was investigated. Both structural and morphological analysis have shown that there is a significant modification in the bilayer film structure and surface following the vacuum annealing process at 450 °C. Electrical properties have been investigated using the Hall Effect measurements as well as the impedance spectroscopy at room temperature. The circuit parameters were determined using an equivalent circuit model fitted from the impedance spectra and suggesting the presence of grain and grain boundary conductions in the bilayer structure. It was found that the film annealed in vacuum for 1 h at 350 °C is optimal in all respects, as it possesses all the desirable characteristics including the lowest resistivity, high porosity and better grain boundary conductivityS

Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations

Standard analysis of variability sources in nanodevices lacks information about the spatial influence of the variability. However this spatial information is paramount for the industry and academia to improve the design of variability-resistant architectures. A recently developed technique, the Fluctuation Sensitivity Map (FSM) is used to analyse the spatial effect of the Line Edge Roughness (LER) variability in key figures-of-merit (FoM) in silicon Gate-All-Around (GAA) nanowire (NW) FETs. This technique gives insight about the local sensitivity identifying the regions inducing the strongest variability into the FoM. We analyse both 22 nm and 10 nm gate length GAA NW FETs affected by the LER with different amplitudes (0.6, 0.7, 0.85 nm) and correlation lengths (10, 20 nm) using in-house 3D quantum-corrected drift-diffusion simulation tool calibrated against experimental or Monte Carlo data. The FSM finds that the gate is the most sensitive region to LER deformations. We demonstrate that the specific location of the deformation inside the gate plays an important role in the performance and that the effect of the location is also dependent on the FoM analysed. Moreover, there is a negligible impact on the device performance if the LER deformation occurs in the source or drain region

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures

Combined nanoscale KPFM characterization and device simulation for the evaluation of the MOSFET variability related to metal gate workfunction fluctuations

In this work, a more realistic approximation based on 2D nanoscale experimental data obtained on a metal layer is presented to investigate the impact of the metal gate polycrystallinity on the MOSFET variability. The nanoscale data (obtained with a Kelvin Probe Force Microscope, KPFM) were introduced in a device simulator to analyze the effect of a TiN metal gate work functions (WF) fluctuations on the MOSFET electrical characteristics. The results demonstrate that the device characteristics are affected not only by the WF fluctuations, but also their spatial distribution, which is specially relevant in very small devices. The effect on these characteristics of the spatial distribution on the gate area of such fluctuations is also evaluatedThis work has been partially supported by the Spanish AEI and ERDF (TEC2016-75151-C3-1-R, TEC2014-53909-REDT and RYC-2017-23312)S

Impact of threshold voltage extraction methods on semiconductor device variability

This paper presents a study of the impact that several widely used threshold voltage (VT) extraction methods have on semiconductor device variability studies. The second derivative (SD), linear extrapolation (LE) and third derivative (TD) extraction techniques have been compared to the standard method used in variability, the constant current criteria (CC). To estimate the influence of these methods on the results, an ensemble of 10.7 nm gate length Si FinFETs affected by RD variability have been simulated. We have shown that variability estimators like the VT, VT and the VT shift, are heavily affected by the selected extraction methodology, with up to 30% differences in the standard deviation. We have demonstrated that being aware of which VT extraction technique has been used in a variability analysis is crucial to properly interpret the results as they may be heavily method-dependentResearch supported by the Spanish Government (TIN2013-41129-P and TIN2016-76373-P) by Xunta de Galicia and FEDER funds (GRC 2014/008) (accreditation 2016-2019, ED431G/08), by the Spanish Ministry of Economy and Competitiveness and FEDER funds (TEC2014-59402-JIN). Authors thank CESGA for the computational facilities provided. The work of G. Indalecio was supported by the Programa de Axudas á Etapa Posdoutoral da Xunta de Galicia under Grant No. 2017/077S

Evaluación del rendimiento de hipervisores usados en infraestructuras cloud que aprovechan la virtualización por hardware

El presente artículo muestra los resultados de un conjunto de benchmarks en anfitriones y máquinas virtuales gestionadas con los hipervisores Xen y KVM, aprovechando el soporte vía hardware para la virtualización del ordenador anfitrión. El objetivo de este trabajo fue determinar qué hipervisor hacia un uso más eficiente de los recursos bajo diferentes condiciones. En los resultados obtenidos, las máquinas virtuales sobre Xen presentaron mejor rendimiento en cálculo; mientras que KVM exhibió un mejor rendimiento en pruebas de acceso al disco y de la red. Se tomaron los datos a partir de comparaciones de variables como tiempo y volumen de transferencia de datos, después de ejecutar las pruebas de rendimiento bajo las mismas condiciones en los diferentes escenarios. Los resultados de este estudio aportan una ruta a seguir para diseñar y optimizar una infraestructura de altas prestaciones basada en IaaS (infraestructura como servicio) para manejo y procesamiento de datos en investigación científicaThis paper presents the results of a set of benchmarks on hosts and virtual machines running Xen and KVM hypervisors, they are leveraging hardware support for virtualization via the host computer. The aim of this study was to determine which hypervisor do more efficient use of resources under different conditions. In the results, the virtual machines on Xen displayed better performance in calculus; while KVM exhibited better performance on tests of disk access and network usage. Data were taken from comparison of variables such as time and volume data transfer, after running performance tests under the same conditions in different scenarios. The results of this study provide a roadmap to design and optimize high-performance infrastructure based on IaaS (infrastructure as a service) for data management and processing in scientific researchS

Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET

In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects with different sizes and shapes on the amplitude of the random telegraph noise (RTN) in Junctionless Fin Field Effect Transistor (FinFET) is modelled and simulated. The RTN amplitude dependence on the number of single charges trapped in a single defect is modelled and simulated too. It is found out that the RTN amplitude in the Junctionless FinFET does not depend on the shape, nor on the size of the single defect area. However, the RTN amplitude in the subthreshold region does considerably depend on the number of single charges trapped in the defectThis research was funded by Ministry of Innovation Development of the Republic of Uzbekistan, grant number OT-F2-67S