Non-recursive max* operator with reduced implementation complexity for turbo decoding

In this study, the authors deal with the problem of how to effectively approximate the max?? operator when having n > 2 input values, with the aim of reducing implementation complexity of conventional Log-MAP turbo decoders. They show that, contrary to previous approaches, it is not necessary to apply the max?? operator recursively over pairs of values. Instead, a simple, yet effective, solution for the max?? operator is revealed having the advantage of being in non-recursive form and thus, requiring less computational effort. Hardware synthesis results for practical turbo decoders have shown implementation savings for the proposed method against the most recent published efficient turbo decoding algorithms by providing near optimal bit error rate (BER) performance

ISIS Facchinetti: A Nearly Zero Energy Retrofit in Italy

The research presented here is about the energy retrofit of an existing high school building close to Varese (Italy). As the building was designed in the 60's with a peculiar architectural language, it has been protected by the conservation authorities. However, the construction system in exposed concrete and the large expanses of single glass make the energy performance of the building very poor. The Provincia di Varese, owner of the building, decided to realize an exemplary retrofit project, which would be the first renovated educational building in Italy in line with the future scenario of Nearly Zero-Energy Building expected from 2019 (2021 for private buildings) by the European Directive 2010/31/UE. In this work energetic and payback analysis are developed to delineate three different preliminary scenarios of intervention. The process has always followed discussions with the conservation authorities, which contributed to the definition of realistic scenarios. Interesting results are obtained: a potential energy demand reduction of 70% can be obtained with the passive solutions proposed; in combination with active strategies (efficient mechanical systems and controls) and with the integration of photovoltaic panels (BiPV), the overall energy need of the building can be reduced to nearly zero

Improving comfort and energy efficiency in a nursery school design process

A new nursery school in Milan was designed in the framework of a national research about low-energy buildings in temperate climates. The design of the case study started from a bioclimatic-approach, considering relationship between building envelope and sun path. In particular, orientation and morphology of the school are optimized (i.e. the building shapes improve solar control; classrooms and offices face South, services face North), the envelope is thermally efficient in both its opaque and transparent parts and overhangs are dimensioned to ensure solar gain in winter and to avoid direct solar radiation during summer season. A set of solutions for optimizing both energy efficiency and comfort conditions has been assessed. A floor radiant system, fed by a groundwater heat pump, has been foreseen and combined with a primary air ventilation system, equipped with heat recovery and managed by CO2 sensors. The school will be also equipped with opening window detectors and presence detectors, coupled by daylighting sensors, for controlling both illumination and thermal energy supply (hot water circulation in the radiant floor pipes and primary air cycle). Further, RE has been integrated in the design for hot water production by evacuated solar collectors placed on the roof of the higher block. As a result, a dynamic simulation made by VisualDOE software assessed 20 kWh/m² of energy heating demand: this value is below national standards foreseen from 2009, referring to the recent Italian implementation of the Energy Performance Building Directive (EPBD)

Improving Energy Efficiency Through Artificial Inertia: Use of Phase Change Materials in Light, Internal Components

Phase Change Materials (PCM’s) are characterised by a large thermal capacity and by melting temperatures close to those associated with human comfort. Thanks to the “artificial inertia” they can give a building, they can be used in components such as wallboards, floors, etc. in order to: - store free heat gains during winter days and release energy during the night; - reduce overheating risks in summer, especially in well-insulated Structure / Envelope constructions (Str/En) with poor thermal capacity (lightweight construction), thanks to the peak-shaving effect; - store off-peak energy – both in winter and summer – in order to have, during the day, a warm / cool surface that contributes to irradiative comfort in winter / summer. An extensive experimental campaign was set up in Ancona (I) and Gävle (S) during the EU-FP5-funded research called C-TIDE (Changeable Thermal Inertia Dry Enclosures), involving Politecnico di Milano, Università Politecnica delle Marche, BMG and three SME. Different configurations were studied and tested on site, allowing to understand the potential for integration of hydrated salt PCM’s in lightweight floors and internal partitions. The experimental campaign included: - prototyping a specific packaging system based on aluminium pouches (the “PCM blanket”); - testing the blanket – both in wall and floors – in experimental boxes with controlled temperature conditions; - testing the implication of sandwiching the blanket in a traditional plasterboard wall from the point of view of assembly procedures, time, everyday use, etc. The results, which were supported by mathematical modelling using the FDM method, show a good potential for integration of PCM’s in light plasterboard components. PCM’s work as a thermal flywheel, reducing the peak loads (for heating and / or cooling) and energy consumption

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Cyclic Redundancy Check (CRC) is often employed in data storage and communications to detect errors. The 3GPP-LTE wireless communication standard uses a 24-bit CRC with every turbo coded frame, thus, the CRC can be exploited to detect residual errors and to enable early stopping of iterations as well. The current state of the art lacks specific CRC implementations for this standard, and most current solutions adopt a fixed degree of parallelism, unsuitable for many turbo decoder architectures. This work proposes a variable parallelism circuit targeting the 3GPP-LTE/LTE-Advanced 24-bit CRC, that can adapt to input data of different sizes. Low complexity is achieved through careful functional sharing among the various parallelisms: comparison with the state of the art shows comparable or superior speed and extremely low complexity

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

This work presents the VLSI hardware implementation of a novel Belief Propagation (BP) algorithm introduced in [1] and named as Analog Digital Belief Propagation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by tracking their parameters. In particular, ADBP can deal with system variables that are discrete and/or wrapped. A variant of ADBP can then be applied for the iterative decoding of a particular class of non binary codes and yields decoders with complexity independent of alphabet size M, thus allowing to construct ecient decoders for digital transmission systems with unbounded spectral eciency. In this work, we propose some simplifications to the updating rules for ADBP algorithm that are suitable for hardware implementation. In addition, we analyze the eect of finite precision on the decoding performance of the algorithm. A careful selection of quantization scheme for input, output and intermediate variables allows us to construct a complete ADBP decoding architecture that performs close to the double precision implementation and shows a promising complexity for large values of M. Finally, synthesis results of the main processing elements of ADBP are reported for 45 nm standard cell ASIC technology

On chip interconnects for multiprocessor turbo decoding architectures

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