Development and characterizations of fine pitch flip-chip interconnection using silver sintering

Flip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Development and characterizations of fine pitch flip-chip interconnection using silver sintering

International audienceFlip-chip interconnects made of silver are promising candidates to overcome the intrinsic limits of solderbased interconnects and match the demand for increased current densities of high-performance microprocessors. Dipbased interconnects have been demonstrated to be a promising approach to form electrical interconnects by sintering paste between copper pillars and pads. However, the quality of the process is limited by residual porosity and poor performances of the sintered joint formed between the pillar and the pad during sintering if a pressure > 50 MPa is not applied in order to decrease the final porosity. In this study, development has been focused on varying key dipping process parameters allowing a pressureless sintering process. Dip-transfer process was optimized on test vehicle and has shown electrical continuity over 700 interconnections with diameter down to 50 µm. We demonstrate high reliability of the process with microstructural observations, tomography X and thermal cycle up to 200 cycles without breakdown

Ultra Wide Micro Bumps Interconnection Matrix for High Energy Particle Detection: Process and Assembly

International audienceMicro pillars and micro bumps interconnections are considered as mature technology for 3-D integration and chip stacking. However, in the framework of high-energy particles detection as ATLAS Large Hadron Collider new tracker project at CERN, very large area array of dense interconnections with an aggressive specification of total thickness variation (TTV) of +/-2μm are required to grant successful detectors assembly process. This paper will first describe the test vehicle that has been designed on purpose for this study. The studies undertaken including lithography mapping, seed layer and electrochemical deposition (ECD) process will then be detailed introducing a model of anode intensity contribution to the overall TTV. To conclude, daisy chain electrical test results and yields after stacking using dieto-wafer approaches will be discussed with respects to process parameters

Flexible Hybrid Electronics Including Ultrathin Strain Sensors or Radio Frequency Identification Dies Manufactured on Wafer Silicon Carrier

International audienceFlexible hybrid electronics (FHE) is becoming a disruptive technology in the packaging of electronic components. Indeed, thanks to the thinness and flexibility of devices, it is conceivable to add a function to any object without changing its aspect. However, this approach faces critical issues such as the management of ultrathin components from different sources and the cost of individual operations. In this paper, a wafer-level packaging (WLP) process for integrated silicon dies coming from various foundries in a flexible label is presented. The process is performed in a microelectronic component manufacturing line on a 200 mm temporary wafer carrier, thus achieving a high level of integration. The purpose of this article is to present results for different hybridization methods of ultrathin silicon dies inside a flexible label. In addition, the process was applied to two demonstrators. The first comprises an ultrathin silicon strain sensor based on a doped crystalline (100) silicon piezoresistive effect that is embedded in a flexible label and bonded to a printed circuit board. When the printed circuit board is mechanically stressed, the die resistances are changed as a result of the piezoresistive effect, and a Wheatstone bridge circuit is used to measure the change in resistance. The second demonstrator is a heterogeneous flexible system including an ultrathin radio frequency identification die integrated within a small flexible label and bonded to a flexible antenna. The functionality of the two demonstrators has been successfully demonstrated

Haptic interface based on an innovative piezo-in-flex piezoelectric patch technology

International audienceThe tremendous development of tactile interface in many customers applications, such as smartphone, leads industrials to study haptic interfaces which allow the user to interact with its environment by the sense of touch. Piezoelectric actuators are commonly used to actuate such interfaces. In this paper, we present a new and innovative technology to integrate collectively commercial piezoceramics into flexible piezoelectric patches able to be integrated on any surface. We glue the flexible patch on a 4×3cm² glass plate to obtain a plug and play interface. A displacement amplitude of 1µm was measured on a Lamb mode at 58.49kHz, using only 20V. A haptic effect was felt by the finger when we modulate at 60Hz the actuation signal, proving the potential of our piezo-in-flex haptic interface