PENGARUH GAYA KEPEMIMPINAN, PARTISIPASI PENGANGGARAN, DAN MOTIVASI, TERHADAP KINERJA MANAJERIAL PADA PT. CITRA YASINDO SETIA

Kinerja manajer dalam suatu perusahaan sangatlah penting karena apabila kinerja manajernya kurang baik, maka dapat dipastikan perusahaan tidak akan mampu bersaing dengan perusahaan lain. Dengan kinerja manajer yang baik diharapkan perusahaan akan mampu bersaing dengan perusahaan lain. Untuk itu ada beberapa faktor yang menyebabkan kinerja manajer tinggi atau rendah dimana dalam penelitian ini peneliti ingin membahas dua faktor yang mungkin dapat mempengaruhi tinggi rendahnya kinerja manajer suatu perusahaan tersebut. Melihat fenomena diatas serta dilandasi dengan penelitian yang menyebutkan bahwa gaya kepemimpinan, partisipasi anggaran dan motivasi mempunyai pengaruh yang besar pada pada kinerja manajer, maka penulis ingin melakukan penelitian dengan tujuan untuk mengukur seberapa besar gaya kepemimpinan, partisipasi anggaran dan motivasi mempengaruhi kinerja manajerial. Atas dasar latar belakang permasalahan tersebut diatas timbul ketertarikan untuk mengadakan penelitian dengan judul : “ Pengaruh Gaya Kepemimpinan, Partisipasi Anggaran Dan Motivasi Terhadap Kinerja Manajer Pada PT. Citra Yasindo Setia”. Populasi dalam penelitian ini adalah Kepala Departemen dan Kepala Bagian yang ikut andil dan berperan penting dalam pengambilan keputusan yang ada di kantor PT. Citra Yasindo Setia Surabaya, yang berjumlah 40 orang dengan sampel sebanyak 40 responden. Penelitian ini berlandaskan pendekatan kuantitatif dengan tekhnik analisis regresi linier berganda. Setelah mengetahui permasalahan, meneliti dan membahas hasil penelitian tentang pengaruh gaya kepemimpinan, partisipasi anggaran dan motivasi terhadap kinerja manajerial maka dapat diambil beberapa kesimpulan sebagai berikut : Secara simultan variabel gaya kepemimpinan, partisipasi anggaran dan motivasi berpengaruh terhadap kinerja manajerial. Secara parsial, variable partisipasi anggaran dan motivasi berpengaruh terhadap kinerja manajerial sedangkan gaya kepemimpinan tidak berpengaruh terhadap kinerja manajerial Kata kunci: Gaya Kepemimpinan, Partisipasi Anggaran, Motivasi Dan Kinerja Manaje

Variability-Aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs) considering various sources of statistical variability. Our simulation approach is based on various simulations techniques to capture the complexity in such ultra-scaled device

Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications

In this paper we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this work

Position-Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors

In this work, we investigated the performance of vertically stacked lateral nanowires transistors (NWTs) considering the effects of series resistance. Also, we consider the vertical positions of the lateral nanowires in the stack and diameter variation of the lateral NWTs as new sources of process variability

Integrated atomistic process and device simulation of decananometre MOSFETs

In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic simulator, which incorporates density gradient quantum corrections. The overall methodology is illustrated in the atomistic process and device simulation of a well behaved 35 nm physical gate length MOSFET reported by Toshiba

Spectral function and quasiparticle weight in the generalized t-J model

We extend to the spectral function an approach which allowed us to calculate the quasiparticle weight for destruction of a real electron Z_c sigma (k) (in contrast to that of creation of a spinless holon Z_h(k) in a generalized $t-J$ model, using the self-consistent Born approximation (SCBA). We compare our results with those obtained using the alternative approach of Sushkov et al., which also uses the SCBA. The results for Z_c sigma (k) are also compared with results obtained using the string picture and with exact diagonalizations of a 32-site square cluster. While on a qualitative level, all results look similar, our SCBA approach seems to compare better with the ED one. The effect of hopping beyond nearest neighbors, and that of the three-site term are discussed.Comment: 7 pages, 6 figure

Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks

Using ensemble Monte Carlo device simulations, this paper studies the impact of interface roughness and soft-optical phonon scattering on the performance of sub-100nm Si and strained Si MOSFETs with different high-k gate stacks. Devices with gate lengths down to 25nm have been investigated

2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application

Traditional memory devices are facing more challenges due to continuous down-scaling. 6T-SRAM suffers from variability [1-2] and reliability [3-4] issues, which introduce cell stability problems. DRAM cells with one transistor, one capacitor (1T1C) struggle to maintain refresh time [5-6]. Efforts have been made to find new memory solutions, such as one transistor (1T) solutions [7-9]. Floating body based memory structures are among the potential candidates, but impact ionization or band-to-band tunnelling (B2BT) limits their refresh time [10]. A recently proposed zero impact ionization and zero subthreshold swing device named Z2FET [9, 11-12] has been demonstrated and is a promising candidate for 1T DRAM memory cell due to technology advantages such as CMOS technology compatibility, novel capacitor-less structure and sharp switching characteristics. In the Z2FET memory operation, refresh frequency is determined by data retention time. Previous research [11-12] is lacking systematic simulation analysis and understanding on the underlying mechanisms. In this paper, we propose a new simulation methodology to accurately extract retention time in Z2FET devices and understand its dependency on applied biases, temperatures and relevant physical mechanisms. Since the stored ‘1’ state in Z2FET is an equilibrium state [9, 11-12] and there is no need to refresh, we will concentrate on state ‘0’ retention. Two types of ‘0’ retention time: HOLD ‘0’ and READ ‘0’ retention time will be discussed separately