19 research outputs found
Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter
No full textThis paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay
Memoria Non Volatile Integrata con Celle di Memoria a Singolo Strato di Polisilicio Programmabile Tramite Iniezione di Portatori di Carica Elettrica Caldi e Cancellabile Tramite Tunneling di Fowler-Nordheim
No full textmemoria non volatile integrata con celle di memoria a singolo strato di polisilicio cancellabile tramite iniezione di elettroni caldi indotti da corrente elettrica da banda a banda e programmabile tramite tunneling di flower-nordheim
No full textEmbedded Non-Volatile Memory With Single Polysilicon Layer Memory Cells Erasable Through Band To Band Tunneling Induced Hot Electron And Programmable Through Fowler-Nordheim Tunneling
No full textEmbedded Non-Volatile Memory With Single Polysilicon Layer Memory Cells Programmable Through Channel Hot Electrons And Erasable Through Fowler-Nordheim Tunneling
No full textEmbedded Non-Volatile Memory With Single Polysilicon Layer Memory Cells Programmable Through Band-To-Band Tunneling-Induced Hot Electron And Erasable Through Fowler-Nordheim Tunneling
No full textA 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification
No full textA reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 μVrms, a 137 μV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS
