Influence of ion irradiation on switching field and switching field distribution in arrays of Co/Pd-based bit pattern media

International audienceWe have used ion irradiation to tune switching field and switching field distribution ͑SFD͒ in polycrystalline Co/Pd multilayer-based bit pattern media. Light He + ion irradiation strongly decreases perpendicular magnetic anisotropy amplitude due to Co/Pd interface intermixing, while the granular structure, i.e., the crystalline anisotropy, remains unchanged. In dot arrays, the anisotropy reduction leads to a decrease in coercivity ͑H C ͒ but also to a strong broadening of the normalized SFD/ H C ͑in percentage͒, since the relative impact of misaligned grains is enhanced. Our experiment thus confirms the major role of misorientated grains in SFD of nanodevice arrays. Today a major research effort in magnetism is targeted toward achieving ultrahigh density data storage with nano-scale magnets. Spin-transfer magnetic random access memory ͑spin-RAM͒ and bit patterned media ͑BPM͒ technologies are currently part of the most promising media. The implementation of both of these technologies relies on achieving in-detail physical understanding and control of the magnetization reversal mechanism in each nanoscopic individual bit to ensure reproducibility of the bit properties in order to avoid write errors. Perpendicular magnetic anisotropy ͑PMA͒ materials, such as polycrystalline Co/Pd, Co/Pt, and Co/Ni multilayers, are believed to be promising materials for both spin-RAM and BPM applications. 1–4 Indeed, they have a well defined high amplitude uniaxial anisotropy that provides good thermal stability while offering low critical current in spin-transfer devices 2 and tunable switching fields in BPM.

Electrical spin injection and detection in Germanium using three terminal geometry

In this letter, we report on successful electrical spin injection and detection in \textit{n}-type germanium-on-insulator (GOI) using a Co/Py/Al$_{2}$O$_{3}$ spin injector and 3-terminal non-local measurements. We observe an enhanced spin accumulation signal of the order of 1 meV consistent with the sequential tunneling process via interface states in the vicinity of the Al$_{2}$O$_{3}$/Ge interface. This spin signal is further observable up to 220 K. Moreover, the presence of a strong \textit{inverted} Hanle effect points at the influence of random fields arising from interface roughness on the injected spins.Comment: 4 pages, 3 figure

On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling

International audienceWith growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core Dynamic Voltage and Frequency scaling (DVFS) is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real Multiple Input Multiple Output (MIMO) Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved

(2009)" Un Nouveau Système d’Instrumentation en Ligne pour la Caractérisation et l’Adaptation Dynamique aux Variations

Résumé — Des dispositifs de surveillance embarqués du processus de fabrication et des paramètres environnementaux sont aujourd’hui indispensables à la lutte contre les effets de la variabilité. Ils permettent également une recherche du point de fonctionnement optimal qui permet de s’affranchir des marges conception, et autorise la baisse de la consommation par des systèmes d’adaptation dynamique. Ce papier présente un nouveau système de surveillance en ligne permettant d’anticiper en temps réel toute violation de temps en observant les variations des marges temporelles. Ce système est composé de structures spécifiques situées près des bascules, couplées avec un générateur de fenêtre de détection localisé sur l’arbre d’horloge. Validation et performances sont données en technologie 45 nm basse consommation et démontrent la faisabilité et l’efficacité de ce système. Mots clés — Variabilité, Surveillance en ligne, Marge temporelle, Compensation, Point de fonctionnement optimal, Basse consommation, adaptation dynamique

On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS

International audienceWith growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved

DPA on quasi delay insensitive asynchronous circuits: concrete results

International audienceThis paper presents the first concrete results of Differential Power Analysis applied on secured Quasi Delay Insensitive asynchronous logic. In fact, the properties of QDI asynchronous circuits (1-of-N encoded data and four-phase handshake protocol) are exploited to improved chip resistance against power analysis. Different architectures and design styles were investigated and analyzed. Three different DES circuits have been designed and fabricated: two in asynchronous technology and one in synchronous to be used as a reference. The results obtained demonstrate that QDI asynchronous circuits significantly improve the DPA resistance. This study also enabled us to identify some limits i.e. residual sources of leakage, that will be addressed in future works

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture

International audienceModern computing applications require more and more data to be processed. Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall. New architectures are currently explored to solve this issue, for both embedded and off-chip memories. Recent techniques that bringing computing as close as possible to the memory array such as, In-Memory Computing (IMC), Near-Memory Computing (NMC), Processing-In-Memory (PIM), allow to reduce the cost of data movement between computing cores and memories. For embedded computing, In-Memory Computing scheme presents advantageous computing and energy gains for certain class of applications. However, current solutions are not scaling to large size memories and high amount of data to compute. In this paper, we propose a new methodology to tile a SRAM/IMC based architecture and scale the memory requirements according to an application set. By using a high level LLVM-based simulation platform, we extract IMC memory requirements for a certain class of applications. Then, we detail the physical and performance costs of tiling SRAM instances. By exploring multi-tile SRAM Place&Route in 28nm FD-SOI, we explore the respective performance, energy and cost of memory interconnect. As a result, we obtain a detailed wire cost model in order to explore memory sizing trade-offs. To achieve a large capacity IMC memory, by splitting the memory in multiple sub-tiles, we can achieve lower energy (up to 78% gain) and faster (up to 49% gain) IMC tile compared to a single large IMC memory instance

Emerging nano-devices for IOT applications

Conference of 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 ; Conference Date: 25 October 2016 Through 28 October 2016; Conference Code:129740International audienceThe miniaturization of systems toward System-On-Chip is a long term trend that will continue after the end of Moore's Law. In the context of Internet-of Things (IoT), this means looking for components, integration schemes and data treatment paradigms enabling the reduction of both power consumption and cost. In this paper we will present some emerging devices for sensing and local data treatment that could enable future energy efficient IOT systems