Gallium oxide and gadolinium gallium oxide insulators on Si δ-doped GaAs/AlGaAs heterostructures

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga<sub>2</sub>O<sub>3</sub> or a stack of Ga<sub>2</sub>O<sub>3</sub> and Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub>. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si delta-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> is included in a stack with 1 nm of Ga<sub>2</sub>O<sub>3</sub> at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ~3 V. However, the inclusion of Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in the gate insulator introduces many oxide states (≤4.70Ã�Â�10<sup>12</sup> cm<sup>âÂ�Â�2</sup>). Transmission electron microscope images of the interface region show that the growth of a Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> layer on Ga<sub>2</sub>O<sub>3</sub> disturbs the well ordered Ga<sub>2</sub>O<sub>3</sub>/GaAs interface. We therefore conclude that while including Gd<sub>0.25</sub>Ga<sub>0.15</sub>O<sub>0.6</sub> in a dielectric stack with Ga<sub>2</sub>O<sub>3</sub> is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga<sub>2</sub>O<sub>3</sub>/GaAs interface and near interface region by introducing roughness and a large number of defect states

180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm

Abstract: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron metrics are the best values reported to date for III-V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions

Monte Carlo simulations of high-performance implant free In_0.3Ga_0.7 nano-MOSFETs for low-power CMOS applications

No abstract available

Sub-micron, Metal Gate, High-к Dielectric, Implant-free, Enhancement-mode III-V MOSFETs

The performance of 300nm, 500nm and 1μm metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-κ (κ=20) dielectric stack grown upon a δ-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 μm to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 μA/μm and extrinsic transconductance of 400 µS/µm are obtained from these devices. Gate leakage current of less than 100pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance submicron enhancement mode III-V MOSFETs reported to date

1 μm gate length, In_0.75Ga_0.25As channel, thin body n-MOSFET on InP substrate with transconductance of 737μS/μm

The first demonstration of implant-free, flatband-mode In<sub>0.75</sub>Ga<sub>0.25</sub>As channel n-MOSFETs is reported. These 1 μm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm<sup>2</sup>/Vs and sheet carrier concentration of 3.3×10<sup>12</sup> cm<sup>-22</sup>, utilise a Pt gate, a high-k dielectric (k≈20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (I<sub>d,sat</sub>) of 933 μA/μm, extrinsic transconductance (g<sub>m</sub>) of 737 μS/μm, gate leakage (I<sub>g</sub>) of 40 pA, and on-resistance (R<sub>on</sub>) of 555 Ωμm. The g<sub>m</sub> and R<sub>on</sub> figures of merit are the best reported to date for any III-V MOSFET

The interface between silicon and a high-k oxide

The ability to follow Moore's Law has been the basis of the tremendous success of the semiconductor industry in the past decades. To date, the greatest challenge for device scaling is the required replacement of silicon dioxide-based gate oxides by high-k oxides in transistors. Around 2010 high-k oxides are required to have an atomically defined interface with silicon without any interfacial SiO2 layer. The first clean interface between silicon and a high-K oxide has been demonstrated by McKee et al. Nevertheless, the interfacial structure is still under debate. Here we report on first-principles calculations of the formation of the interface between silicon and SrTiO3 and its atomic structure. Based on insights into how the chemical environment affects the interface, a way to engineer seemingly intangible electrical properties to meet technological requirements is outlined. The interface structure and its chemistry provide guidance for the selection process of other high-k gate oxides and for controlling their growth. Our study also shows that atomic control of the interfacial structure can dramatically improve the electronic properties of the interface. The interface presented here serves as a model for a variety of other interfaces between high-k oxides and silicon.Comment: 10 pages, 2 figures (one color

Enhancement Mode n-MOSFET with High-κ Dielectric on GaAs Substrate

In this paper, we report MOS heterostructures grown by molecular beam epitaxy on III-V substrates, employing a high-κ dielectric stack comprised of gallium oxide and gadolinium gallium oxide. Mobilities exceeding 12,000 and 6,000 cm2/Vs, for sheet carrier concentration ns of about 2.5x1012 cm-2 were measured on MOSFET structures on InP and GaAs substrates, respectively. These structures were designed for enhancement mode operation and include a 10 nm thick strained InGa1-xAs channel layer with In mole fraction x of 0.3 and 0.75 on GaAs and InP substrates, respectively

Molecular beam epitaxy of highly crystalline GeSnC using CBr4 at low temperatures

Tensile-strained pseudomorphic Ge1–x–ySnxCy was grown on GaAs substrates by molecular beam epitaxy using carbon tetrabromide (CBr4) at low temperatures (171–258 °C). High resolution x-ray diffraction reveals good crystallinity in all samples. Atomic force microscopy showed atomically smooth surfaces with a maximum roughness of 1.9 nm. The presence of the 530.5 cm−1 local vibrational mode of carbon in the Raman spectrum verifies substitutional C incorporation in Ge1–x–ySnxCy samples. X-ray photoelectron spectroscopy confirms carbon bonding with Sn and Ge without evidence of sp2 or sp3 carbon formation. The commonly observed Raman features corresponding to alternative carbon phases were not detected. Furthermore, no Sn droplets were visible in scanning electron microscopy, illustrating the synergy in C and Sn incorporation and the potential of Ge1–x–ySnxCy active regions for silicon-based lasers.The authors acknowledge support from the National Science Foundation under Grant Nos. DMR-1508646, CBET-1438608, and PREM DMR-2122041, the Center for Dynamics and Control of Materials is supported by the National Science Foundation under Award No. DMR-1720595, and additional support by the University of Texas at Austin.Center for Dynamics and Control of Material