2 research outputs found
Circuit Design for Predictive Maintenance
Industry 4.0 has become a driver for the entire manufacturing industry. Smart
systems have enabled 30% productivity increases and predictive maintenance has
been demonstrated to provide a 50% reduction in machine downtime. So far, the
solution has been based on data analytics which has resulted in a proliferation
of sensing technologies and infrastructure for data acquisition, transmission
and processing. At the core of factory operation and automation are circuits
that control and power factory equipment, innovative circuit design has the
potential to address many system integration challenges. We present a new
circuit design approach based on circuit level artificial intelligence
solutions, integrated within control and calibration functional blocks during
circuit design, improving the predictability and adaptability of each component
for predictive maintenance. This approach is envisioned to encourage the
development of new EDA tools such as automatic digital shadow generation and
product lifecycle models, that will help identification of circuit parameters
that adequately define the operating conditions for dynamic prediction and
fault detection. Integration of a supplementary artificial intelligence block
within the control loop is considered for capturing non-linearities and
gain/bandwidth constraints of the main controller and identifying changes in
the operating conditions beyond the response of the controller. System
integration topics are discussed regarding integration within OPC Unified
Architecture and predictive maintenance interfaces, providing real-time updates
to the digital shadow that help maintain an accurate, virtual replica model of
the physical system.Comment: 4 pages, 4 figures, position pape
An integrated 10MHz 3 States Buck converter for fast transient response in 180nm CMOS
International audienceThis paper presents a three-state buck converter using a "bypass" state which role is to reduce the amount of energy in the inductor by cutting it off the circuit. The addition of that state makes the converter behave as an order 1 system and thus achieves automatic and seamless loop transition during load transient to achieve small voltage under/overshoot and short recovery time. The proposed chip has been implemented in CMOS 0.18 um and uses 2.25 mm2 area. A 88 % peak efficiency is achieved over 0 to 1A range of load at 1.2 V output voltage. It responds to a 1A load transient in 300 ns while switching at 10 MHz, with a 20mV overshoot