EDACs and test integration strategies for NAND flash memories

Mission-critical applications usually presents several critical issues: the required level of dependability of the whole mission always implies to address different and contrasting dimensions and to evaluate the tradeoffs among them. A mass-memory device is always needed in all mission-critical applications: NAND flash-memories could be used for this goal. Error Detection And Correction (EDAC) techniques are needed to improve dependability of flash-memory devices. However also testing strategies need to be explored in order to provide highly dependable systems. Integrating these two main aspects results in providing a fault-tolerant mass-memory device, but no systematic approach has so far been proposed to consider them as a whole. As a consequence a novel strategy integrating a particular code-based design environment with newly selected testing strategies is presented in this pape

Handling robot constraints within a Set-Based Multi-Task Priority Inverse Kinematics Framework

Set-Based Multi-Task Priority is a recent framework to handle inverse kinematics for redundant structures. Both equality tasks, i.e., control objectives to be driven to a desired value, and set-bases tasks, i.e., control objectives to be satisfied with a set/range of values can be addressed in a rigorous manner within a priority framework. In addition, optimization tasks, driven by the gradient of a proper function, may be considered as well, usually as lower priority tasks. In this paper the proper design of the tasks, their priority and the use of a Set-Based Multi-Task Priority framework is proposed in order to handle several constraints simultaneously in real-time. It is shown that safety related tasks such as, e.g., joint limits or kinematic singularity, may be properly handled by consider them both at an higher priority as set-based task and at a lower within a proper optimization functional. Experimental results on a 7DOF Jaco$^2

Cartilage contact pressure in the knee during walking in healthy and degenerated conditions: a subject-specific Finite Element modeling analysis

L’osteoartrosi inficia gravemente la biomeccanica di ginocchio. L’individuazione precoce è cruciale per limitare danni alla cartilagine e il suo processo degenerativo. Nella ricerca sull’osteoartrosi, i modelli computazionali hanno un ruolo importante nell’analisi quantitativa della distribuzione in-vivo dei carichi nei tessuti. Lo scopo di questo studio è analizzare le pressioni di contatto sulla cartilagine di ginocchio nel cammino in condizioni sane e patologiche, utilizzando un modello agli elementi finiti personalizzato da MRI. Il modello con cartilagine sana include: articolazione tibiofemorale con relative ossa, cartilagini, legamenti e muscoli, e articolazione d’anca. La cartilagine è modellata come iperelastica, e il contatto tra cartilagini senza attrito. Sono stati sviluppati due modelli con cartilagine degenerata: con difetto cartilagineo, e con materiale più cedevole intorno al difetto. L’analisi è stata condotta per la fase di appoggio del ciclo del passo. Sono state confrontate le pressioni di contatto del modello sano con quelle ottenute da un modello multi-corpo precedentemente sviluppato, e sono state analizzate le differenze tra modelli con cartilagine sana e degenerata. Abbiamo ottenuto pressioni di contatto simili tra il nostro modello sano e quello multicorpo (R^2=0.94), e ciò valida indirettamente quest’ultimo. Abbiamo riscontrato che un difetto cartilagineo induce un significativo aumento di pressione fino al 75% in confronto a condizioni sane, in particolare intorno al difetto. L’indebolimento nelle proprietà materiali induce poi una diversa distribuzione di pressione a seguito di una maggiore area di contatto. Nonostante i limiti, questo studio risulta rilevante nella comprensione dei meccanismi di degenerazione cartilaginea. La forza del modello risiede nell’approccio MRI-based ed open-source e nella parametrizzazione del modello per studiare molteplici attività motorie ed interazioni tra i tessuti

Software-Based Self-Test of Set-Associative Cache Memories

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: 1) test patterns which must be composed of valid instruction opcodes and 2) test result observability: the results can only be observed through the results of executed instructions. For these reasons, the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologie

Online self-repair of FIR filters

Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs

A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems

Nowadays, systems-on-chip are commonly equipped with reconfigurable hardware. The use of hybrid architectures based on a mixture of general purpose processors and reconfigurable components has gained importance across the scientific community allowing a significant improvement of computational performance. Along with the demand for performance, the great sensitivity of reconfigurable hardware devices to physical defects lead to the request of highly dependable and fault tolerant systems. This paper proposes an FPGA-based reconfigurable software architecture able to abstract the underlying hardware platform giving an homogeneous view of it. The abstraction mechanism is used to implement fault tolerance mechanisms with a minimum impact on the system performanc

AFSM-based deterministic hardware TPG

This paper proposes a new approach for designing a cost-effective, on-chip, hardware pattern generator of deterministic test sequences. Given a pre-computed test pattern (obtained by an ATPG tool) with predetermined fault coverage, a hardware Test Pattern Generator (TPG) based on Autonomous Finite State Machines (AFSM) structure is synthesized to generate it. This new approach exploits "don't care" bits of the deterministic test patterns to lower area overhead of the TPG. Simulations using benchmark circuits show that the hardware components cost is considerably less when compared with alternative solution

Static analysis of SEU effects on software applications

Control flow errors have been widely addressed in literature as a possible threat to the dependability of computer systems, and many clever techniques have been proposed to detect and tolerate them. Nevertheless, it has never been discussed if the overheads introduced by many of these techniques are justified by a reasonable probability of incurring control flow errors. This paper presents a static executable code analysis methodology able to compute, depending on the target microprocessor platform, the upper-bound probability that a given application incurs in a control flow error

Memory read faults: taxonomy and automatic test generation

This paper presents an innovative algorithm for the automatic generation of March tests. The proposed approach is able to generate an optimal March test for an unconstrained set of memory faults in very low computation time. Moreover, we propose a new complete taxonomy for memory read faults, a class of faults never carefully addressed in the past

A watchdog processor to detect data and control flow errors

A watchdog processor for the MOTOROLA M68040 microprocessor is presented. Its main task is to protect from transient faults caused by SEUs the transmission of data between the processor and the system memory, and to ensure a correct instructions' flow, just monitoring the external bus, without modifying the internal architecture of the M68040. A description of the principal procedures is given, together with the method used for monitoring the instructions' flow