The Corn Club I and II

April, 1923.Includes index.Cover title

Description of a solder pulse generator for the single step formation of ball grid arrays

The traditional geometry for surface mount devices is the peripheral array where the leads are on the edges of the device. As the technology drives towards high input/output (I/O) count (increasing number of leads) and smaller packages with finer pitch (less distance between peripheral leads), limitations on peripheral surface mount devices arise. The leads on these fine pitch devices are fragile and can be easily bent. It becomes increasingly difficult to deliver solder past to leads spaced as little as 0.012 inch apart. Too much solder mass can result in bridging between leads while too little solder can contribute to the loss of mechanical and electrical continuity. A solution is to shift the leads from the periphery of the device to the area under the device. This scheme is called areal array packaging and is exemplified by the ball grid array (BGA) package. A system has been designed and constructed to deposit an entire array of several hundred uniform solder droplets onto a printed circuit board in a fraction of a second. The solder droplets wet to the interconnect lands on a pc board and forms a basis for later application of a BGA device. The system consists of a piezoelectric solder pulse unit, heater controls, an inert gas chamber and an analog power supply/pulse unit

Computational continuum modeling of solder interconnects: Applications

The most commonly used solder for electrical interconnections in electronic packages is the near eutectic 60Sn-40Fb alloy. This alloy has a number of processing advantages (suitable melting point of 183C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue), the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes the prediction of solder joint lifetime complex. A viscoplastic, microstructure dependent, constitutive model for solder, which is currently under development, was implemented into a finite element code. With this computational capability, the thermomechanical response of solder interconnects, including microstructural evolution, can be predicted. This capability was applied to predict the thermomechanical response of a mini ball grid array solder interconnect. In this paper, the constitutive model will first be briefly discussed. The results of computational studies to determine the thermomechanical response of a mini ball grid array solder interconnects then will be presented

Life prediction modeling of solder interconnects for electronic systems

A microstructurally-based computational simulation is presented that predicts the behavior and lifetime of solder interconnects for electronic applications. This finite element simulation is based on an internal state variable constitutive model that captures both creep and plasticity, and accounts for microstructural evolution. The basis of the microstructural evolution is a simple model that captures the grain size and microstructural defects in the solder. The mechanical behavior of the solder is incorporated into the model in the form of time-dependent viscoplastic equations derived from experimental creep tests. The unique aspect of this methodology is that the constants in the constitutive relations of the model are determined from experimental tests. This paper presents the constitutive relations and the experimental means by which the constants in the equations are determined. The fatigue lifetime of the solder interconnects is predicted using a damage parameter (or grain size) that is an output of the computer simulation. This damage parameter methodology is discussed and experimentally validated

Computational continuum modeling of solder interconnects

The most commonly used solder for electrical interconnections in electronic packages is the near eutectic 60Sn-40Pb alloy. This alloy has a number of processing advantages (suitable melting point of 183 C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue), the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes prediction of solder joint lifetime complex. A viscoplastic, microstructure dependent, constitutive model for solder which is currently in development was implemented into a finite element code. With this computational capability, the thermomechanical response of solder interconnects, including microstructural evolution, can be predicted. This capability was applied to predict the thermomechanical response of various leadless chip carrier solder interconnects to determine the effects of variations in geometry and loading. In this paper, the constitutive model will first be briefly discussed. The results of computational studies to determine the effect of geometry and loading variations on leadless chip carrier solder interconnects then will be presented

Microstructurally based finite element simulation of solder joint behavior

The most commonly used solder for electrical interconnects in electronic packages is the near eutectic 60Sn-40Pb alloy. This alloy has a number of processing advantages (suitable melting point of 183C and good wetting behavior). However, under conditions of cyclic strain and temperature (thermomechanical fatigue) the microstructure of this alloy undergoes a heterogeneous coarsening and failure process that makes the prediction of solder joint lifetime complex. A finite element simulation methodology to predict solder joint mechanical behavior, that includes microstructural evolution, has been developed. The mechanical constitutive behavior was incorporated into the time dependent internal state variable viscoplastic model through experimental creep tests. The microstructural evolution is incorporated through a series of mathematical relations that describe mass flow in a temperature/strain environment. The model has been found to simulate observed thermomechanical fatigue behavior in solder joints

Modeling non-isothermal intermetallic layer growth in the 63Sn-37Pb/Cu system

A model describing diffusion-controlled growth of multiple intermetallic layers and the displacement of the interfaces between layers was developed and implemented in a 1-D computer code based on method-of-lines. The code was applied to analysis of intermetallic layer growth in isothermal solder aging experiments performed with 100 Sn/Cu and 63Sn-37Pb/Cu solder-substrate systems. Analyses indicated that intermetallic layer growth was consistent with a bulk diffusion mechanism involving Cu and/or Sn. In this work, nonisothermal solder-aging experiments were done with the 63Sn- 37Pb/Cu system using two temperature histories (4 cycles/day between 223-443 K, and 72 cycles/day between 223-443 K). Isothermal experiments were also done at 443 K. Thickness of Cu{sub 3}Sn and Cu{sub 6}Sn{sub 5} intermetallic layers were determined vs time for each temperature history. An updated version of the model and code were used to predict the intermetallic layer growth. Arrhenius expressions for diffusion coefficients in both Cu3Sn and Cu6Sn5 layers were determined. Agreement between prediction and experiment was generally good. In some cases, predicted layer growth was less than experiment, but within error. This paper describes the nonisothermal experiments and a comparison of predicted and observed layer growth vs time