Managing Waiting Times to Predict No-shows and Cancelations at a Children’s Hospital

Purpose: Since long waits in hospitals have been found to be related to high rates of no-shows and cancelations, managing waiting times should be considered as an important tool that hospitals can use to reduce missed appointments. The aim of this study is to analyze patients’ behavior in order to predict no-show and cancelation rates correlated to waiting times. Design/methodology/approach: This study is based on the data from a US children’s hospital, which includes all the appointments registered during one year of observation. We used the call-appointment interval to establish the wait time to get an appointment. Four different types of appointment-keeping behavior and two types of patients were distinguished: arrival, no-show, cancelation with no reschedule, and cancelation with reschedule; and new and established patients. Findings: Results confirmed a strong impact of long waiting times on patients’ appointment-keeping behavior, and the logarithmic regression was found as the best-fit function for the correlation between variables in all cases. The correlation analysis showed that new patients tend to miss appointments more often than established patients when the waiting time increases. It was also found that, depending on the patients’ appointment distribution, it might get more complicated for hospitals to reduce missed appointments as the waiting time is reduced. Originality/value: The methodology applied in our study, which combines the use of regression analysis and patients’ appointment distribution analysis, would help health care managers to understand the initial implications of long waiting times and to address improvement related to patient satisfaction and hospital performance.Peer Reviewe

Challenges in mixed-signal IC design of CNN chips in submicron CMOS

Summary form only given. The contrast observed between the performance of artificial vision machines and "natural" vision system is due to the inherent parallelism of the former. In particular, the retina combines image sensing and parallel processing to reduce the amount of data transmitted for subsequent processing by the following stages of the human vision system. Industrial applications demand CMOS vision chips capable of flexible operation, with programmable features and standard interfacing to conventional equipment. The CNN Universal Machine (CNN-UM) is a powerful methodological framework for the systematic development of these chips. Basic system-level targets in the design of these chips are to increase the cell density and operation speed. As the technology scales down to submicron all the lateral dimensions decrease by the scaling factor /spl lambda/, and the vertical dimensions scale as /spl lambda//sup -a/, where a is typically around 1/2. Ideally, cell density /spl prop//spl lambda//sup 2/ and time constant /spl prop//spl lambda//sup -2/. The article explains why this is not strictly true, and addresses the challenges involved in the design of CNN chips in submicron technologies.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Fretting-Fatigue Analysis of Shot-Peened Al 7075-T651 Test Specimens

Shot peening is a mechanical treatment that induces several changes in the material: surface roughness, increased hardness close to the surface, and, the most important, compressive residual stresses. This paper analyzes the effect of this treatment on alloy Al 7075-T651 in the case of fretting fatigue with cylindrical contact through the results of 114 fretting fatigue tests. There are three independent loads applied in this type of test: a constant normal load N, pressing the contact pad against the specimen; a cyclic bulk stress σ in the specimen; and a cyclic tangential load Q through the contact. Four specimens at each of 23 different combinations of these three parameters were tested—two specimens without any treatment and two treated with shot peening. The fatigue lives, contact surface, fracture surface, and residual stresses and hardness were studied. Improvement in fatigue life ranged from 3 to 22, depending on fatigue life. The relaxation of residual-stress distribution related to the number of applied cycles was also measured. Finally, another group of specimens treated with shot peening was polished and tested, obtaining similar lives as in the tests with specimens that were shot-peened but not polished.Junta de Andalucía P12-TEP-263

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-μm CMOS technology.European Union IST 2001 38097Ministerio de Ciencia y Tecnología TIC 2003 09817 C02 01Office of Naval Research (USA) N00014021088

Returning to the straddle and the nature of the contractual link of managerial high places and social managers

El presente trabajo está dedicado a un estudio eminentemente jurisprudencial del encuadramiento y las vicisitudes de la relación laboral de altos directivos y administradores sociales. Su objetivo es arrojar luz sobre un tema controvertido y de máxima actualidad práctica.This work is related to the study of the case law regarding the straddle and the vicissitudes of the labour relation of managerial high places and social managers. Its primary focus is to throw light on a complex topic and of maximum practical current importance

International Legal Analysis of The Boundary Delimitation of The Canarian Waters

El presente trabajo está dedicado al estudio del marco jurídico internacional aplicable a la delimitación y protección ambiental de los espacios marítimos del Archipiélago Canario. Su objetivo principal es arrojar luz sobre un tema complejo y de candente actualidad en Canarias.The present work is related to the study of the international legal framework applicable to the boundary and environmental protection of the marine spaces of the Canary Archipelago. Its primary focus is to throw light on a complex subject and of increasing importance nowadays in the Canary Islands

A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors

This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the implementation of general massively-parallel analog processors in CMOS technology. It is specially suited for translationally-invariant processing arrays with local connectivity, and results in a significant reduction in area occupation and power dissipation of the basic processing units. This allows higher integration densities and therefore, permits the integration of larger arrays on a single chip.Comisión Interministerial de Ciencia y Tecnología TIC96- 1392-C02-0

A mixed-signal early vision chip with embedded image and programming memories and digital I/O

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (∼ 7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame

CMOS optical-sensor array with high output current levels and automatic signal-range centring

A CMOS compatible photosensor with high output current levels, and an area-efficient scheme for automatic signal-range centring according to illumination conditions are presented. The high output current levels allow the use of these devices in continuoustime asynchronous imagers, as well as in high-sampling-frequency applications

Robust symmetric multiplication for programmable analog VLSI array processing

This paper presents an electrically programmable analog multiplier. The circuit performs the multiplication between an input variable and an electrically selectable scaling factor. The multiplier is divided in several blocks: a linearized transconductor, binary weighted current mirrors and a differential to single-ended current adder. This paper shows the advantages introduced using a linearized OTA-based multiplier. The circuit presented renders higher linearity and symmetry in the output current than a previously reported single-transistor multiplier. Its inclusion in an array processor based on CNN allows for a more accurate implementation of the processing model and a more robust weight distribution scheme than those found in previous designs.Office of Naval Research (USA) N-00014- 02-1-0884Ministerio de Ciencia y Tecnología TIC2003-09817-C02-0