A case for code-representative microbenchmarks

Microbenchmarks are fundamental in the design of a microarchitecture. They allow rapid evaluation of the system, while incurring little exploration overhead. One key design aspect is the thermal design point (TDP), the maximum sustained power that a system will experience in typical conditions. Designers tend to use hand-coded microbenchmarks to provide an estimation for TDP. In this work we make the case for a systematic methodology to automatically generate code-representative microbenchmarks that can be used to drive the TDP estimation

Cosmic Bell Test using Random Measurement Settings from High-Redshift Quasars

In this Letter, we present a cosmic Bell experiment with polarization-entangled photons, in which measurement settings were determined based on real-time measurements of the wavelength of photons from high-redshift quasars, whose light was emitted billions of years ago, the experiment simultaneously ensures locality. Assuming fair sampling for all detected photons and that the wavelength of the quasar photons had not been selectively altered or previewed between emission and detection, we observe statistically significant violation of Bell's inequality by $9.3$ standard deviations, corresponding to an estimated $p$ value of $\lesssim 7.4 \times 10^{-21}$. This experiment pushes back to at least $\sim 7.8$ Gyr ago the most recent time by which any local-realist influences could have exploited the "freedom-of-choice" loophole to engineer the observed Bell violation, excluding any such mechanism from $96\%$ of the space-time volume of the past light cone of our experiment, extending from the big bang to today.Comment: 9 pages, 4 figures, plus Supplemental Material (16 pages, 8 figures). Matches version to be published in Physical Review Letter

An academic RISC-V silicon implementation based on open-source components

©2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) ´ from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedPostprint (author's final draft