Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1]

Setting prices for reproductive health services in a public hospital in Guatemala

The Hospital Roosevelt is Guatemala’s largest hospital, and serves as a referral and training facility for the entire country. Within the Hospital Roosevelt, the Department of Obstetrics and Gynecology established a Reproductive Health Unit (RHU) to offer family planning information and services to obstetrics inpatients and OB/GYN outpatient clients, and to serve as a training site for medical residents completing their OB/GYN rotations. Hospital administrators requested assistance from the Frontiers in Reproductive Health (FRONTIERS) program to help establish a fee schedule for the RHU, with the goal of paying its own personnel costs after one year of operation. The FRONTIERS study found that the RHU was easily earning enough revenue to break even, but was unable to meet demand for tubal ligation because of limited access to surgical facilities. Several options were outlined for increasing production of tubal ligation while continuing to generate revenue to cover the expenditures for which the RHU is responsible

Class AB cascode current memory cell.

The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell

The application of IDDX test strategies in analogue and mixed signal IC's

Supply Current Testing (IDDQ) has become an important defect oriented test strategy for digital IC products. The technique takes advantage of the low quiescent supply current drawn by static CMOS circuits relative to the current consumption during state changes. However, in analogue and mixed signal IC’s this condition can rarely be observed, as in most circuits, steady state currents depend on the biasing conditions and the circuit design. This paper reviews analogue current monitoring proposals, investigates some of the problems related to the use of these techniques and attempts to categorise a number of analogue design styles against the probable suitability for current testing methodologies

A design-for-test structure for optimising analogue and mixed signal IC test

A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a “swap amp” is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics