7 research outputs found

    CMOS programmable analog memory-cell array using floating-gate circuits

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    Journal ArticleThe complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells

    An analog VLSI model of muscular contraction

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    © 2003 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other worksDOI: 10.1109/TCSII.2003.813593We have developed analog VLSI circuits to model the behavior demonstrated by biological sarcomeres, the force generating components of muscle tissue. The circuits are based upon the mathematical description of crossbridge populations developed by A. F. Huxley (1957). We have implemented the sarcomere circuit using a standard 1.2 μm process, and have demonstrated the nonlinear transient behaviors exhibited by biological muscle

    ACC/AHA guidelines for ambulatory electrocardiography

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