High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

International audienceIn this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the post-layout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node

SamurAI: a 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to-Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency

International audienceIoT node application requirements are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). This paper presents a versatile IoT node covering this gap in processing and energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. The AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with 207ns wake-up time optimized for short sporadic computing. OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) and crypto accelerators for more complex tasks. The node can perform up to 36GOPS while achieving 15,000x reduction from peak-to-idle power consumption. The interest of this versatile architecture is demonstrated with 105μW daily average power on an applicative classification scenari