Effective field and universal mobility in high-k metal gate UTBB-FDSOI devices

session 1: parameter extractionInternational audienceThis paper aims at reviewing experimental and theoretical behaviors of universal mobility in high-k metal gate UTBB-FDSOI devices. Based on split-CV mobility measurements, the parameter η, characterizing the effective field, has been extracted for a large range of back voltages and temperatures in devices with various equivalent oxide thicknesses. We demonstrated that a nearly universal trend for the mobility with respect to the effective field can be obtained in the front inversion regime but is difficult to obtain in the back channel inversion regime. Keywords—FDSOI, universal mobility, effective field, coefficient η

Full-quantum study of AlGaN/GaN HEMTs with InAlN back-barrier

session: Organic and Novel Material Devices (7.2)International audienceA full-quantum simulation of the electron transport in the two-dimensional electron gas (2DEG) of a AlGaN/GaN/InAlN/GaN heterostructure is carried out using the non-equilibrium Green function (NEGF) approach. The introduction of the InAlN back-barrier and the use of a ultra-thin GaN layer for the charge transport considerably entangles the physics of the device. A full-quantum approach is then deemed necessary to shed light on the transport properties of these devices. Gate-length and channel-thickness scaling are studied to assess the impact of confinement effects on the elctrostatic integrity of the device

Evidence of fast and low-voltage A2RAM ‘1’ state programming

session Memoty (7.4)International audienceFor the first time, we demonstrate a new concept for programming the `1' state in A2RAM based on the impact ionization in the bridge, which can be assisted by the band-to-band tunneling effect in the top part of the silicon film. This new programming method reduces the programming voltage and writing time, making the A2RAM suitable as 1T-DRAM. Evidenced through TCAD simulation, the feasibility in matrix environment is also demonstrated

Back gate impact on the noise performances of 22FDX fully-depleted SOI CMOS

International audienceUltra-Thin-Body and Back-oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) MOSFETs are the most recent and advanced Silicon-On-Insulator (SOI) architecture proposed to overcome the down-scaling limitations of traditional bulk devices. The UTBB-FDSOI architecture has already been proved very attractive for RF-mmW circuits thanks to the excellent reported RF figure of merits (FOMs).In this article, we report on an experimental investigation of the back gate biasing impact on the high-frequency (HF) noise performances of an advanced 22 nm UTBB-FDSOI technology developed by GLOBALFOUNDRIES. For the lower gate voltages, the back gate biasing was shown to decrease by one third the equivalent noise resistance (Rn). Moreover, a 3 dB increase for the associated gain (Ga) was achieved at Vg=0.3V. A relaxed contacted-poly-pitch was also shown to decrease Rn by 11%

Atomistic investigation of the impact of stress during solid phase epitaxial regrowth

International audienceAn atomistic model to account for the impact of stress during solid phase epitaxial regrowth (SPER) is proposed. This model is based on the lattice kinetic Monte Carlo method. It has been compared with experimental data of regrowth velocity as a function of hydrostatic and non‐hydrostatic stresses.In particular, it permits to provide a physical explanation of the observations upon in‐plane uniaxial stress based on the assumption that {100} events occur through a dual‐timescale atomistic mechanism. Our model also catches the fact that compressive normal uniaxial stress and hydrostatic pressure result in an enhancement of the regrowth velocity with a similar activation volume

Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit

International audienceSingle Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells [1,2]. We can find models which describe SET in literature [1, 5] but they are not compact (i e. physical model implemented in Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging. Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect of SET on SRAM cell and shift register

Optimization guidelines of A2RAM cell performance through TCAD simulations

session: Future Devices (12.4)International audienceA2RAM belongs to the 1T-DRAM family and is a potential candidate to replace the traditional 1T/1C- DRAM [1-2]. In this paper, we propose a TCAD simulation [3] methodology to assess A2RAM performance, validated through experimental measurement. It is then used to provide further insight in A2RAM and optimization guidelines