Transistor sizing methodology for low noise charge sensitive amplifier with input transistor working in moderate inversion

In this paper noise contribution of current source transistors and sizing methodology in charge sensitive amplifier for application in the front-end readout electronics is presented. In modern deep-submicron technologies, MOS transistor operating region tends to shift from strong inversion to moderate inversion, this makes traditional square-law MOS device modeling not applicable anymore. Thus a simplified EKV model, which is quite successful in all CMOS operating regions, has been adopted to develop a new analytical methodology to optimize geometry of current source transistors so that the noise contribution from these transistors is only a fraction of input transistor noise. A charge sensitive amplifier based on dual PMOS cascode structure is designed by adopting this current source transistor sizing methodology, and has been simulated using 130nm CMOS technology. The proposed methodology and noise contribution from current source transistors have been found in good agreement with simulation results using deep-submicron CMOS technology

Design of a low-noise low-power front-end readout circuit for neutron detection using 130nm CMOS technology

Neutron detectors are used to detect neutron particles in science, security, and other applications. A typical neutron detection system consists of detector itself and frontend readout electronics. Since neutron detector does not have its operational setting in terms of signal speed and output signal gain, it requires a suitable readout electronics which capable of accepting wide range and fast input signal. Front-end readout electronics designed in CMOS technology has enabled highly integrated readout channels which increases the resolution of neutron detection. However, due to technology down scaling and the requirements for low power design, the transistor operating region tends to shift from strong inversion to moderate inversion, and the classic MOSFET modelling, also known as “square law” is not applicable anymore. Hence, a more accurate MOSFET modelling is needed in deep submicron CMOS technology to design the front-end readout circuit. Another one significant challenge in designing front-end readout circuit is to design low noise while at the same time minimizing the power consumption. This study presents the design of a low noise and low power front-end readout circuit that is implemented in 130nm CMOS technology. The front-end readout system which has been designed in this study was composed of two parts: (a) pre - amplifier and (b) amplifier pulse shaper. A simplified Enz Krummenacher Vittoz model or known as EKV model was studied and applied in this work. The model is quite successful in all CMOS operating region, especially in moderate inversion to predict the MOSFET behaviour. The input transistor of front-end system was carefully designed which is critical to readout channel noise performance. A p-channel MOSFET is selected for input transistor due to its lower flicker noise coefficient, and the geometries of all transistors in preamplifier are optimized for minimum noise contribution to the system. The input transistor is made to operate in moderate inversion which is good trade-off between system speed and power consumption. A folded cascode structure is designed for preamplifier to boost the gain and bandwidth. A first order pulse shaper with pole zero cancellation circuit is designed with short peaking time to meet fast counting rate requirements. A series of simulation including post-layout simulation was carried out to measure front-end system equivalent noise charge, power consumption, charge gain, peaking time, high counting rate and linearity. Results showed that the front-end readout channel designed in CMOS technology in this work has a good electronic noise performance with only an equivalent noise charge of 183 electrons for a detector capacitance of 1pF. The channel power consumption is only about 0.89mW with a charge gain of 3.6mV/fC. Peaking time is around 104 nanoseconds and it is capable of accepting high count rate input signal of 333 kHz with less than 5% output signal distortion. These results showed that the designed front-end readout circuit implemented in 130nm CMOS technology with input transistor working in moderate inversion has good electronic noise performance, high counting rate while reducing the total power consumption. It also shows that the front-end readout system is suitable for using in neutron particle detection system