Colloidal particles as noise source for random number generation

In this work, we investigate colloidal particle patterns as a possible noise source for random number generation. We systematically analyze the minimum entropy of the noise source over different particle concentrations of {1, 3, 5, 7, 10, 12, 15} mg/ml according to the recommendations of the National Institute of Standards and Technology Special Publication 800-90B. The estimated minimum entropy of the non-independent and identically distributed particle pattern noise source is Hmin = 0.5896/1 bit at a particle amount of 5 mg/ml. For further entropy extraction on the noise source data, the secure hash algorithm is used to construct an entropy source. The randomness of the derived entropy source is verified according to the National Institute of Standards and Technology Special Publication 800-22 Rev. 1a and the accompanying statistical test suite. The entropy source passes all randomness tests of the statistical test suite and shows an estimated minimum entropy of Hmin = 0.9992/1 bit

A Comprehensive Guide to Fully Inkjet‐Printed IGZO Transistors

In this concise review, the recent advancements in fully inkjet-printed (IJP) indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) over the past years are discussed. IGZO has replaced hydrogenated amorphous silicon (a-Si:H) as the primary channel material for liquid-crystal display TFTs and has gained further attention due to the solution processability of IGZO inks. Despite the longstanding practice of printing IGZO for approximately fifteen years, the realization of fully inkjet-printed devices, including both dielectric and electrode components, represents a recent milestone in research, potentially heralding a cost-effective era for IGZO transistors. In this review, following an introductory exposition of IGZO, the focus is on the different ink formulations, currently deployed for solution-processed IGZO devices, the intricacies of the printing procedure involved are delineated, and ongoing research endeavors pertaining to the printing of dielectrics and electrodes for such devices are expounded upon

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 μ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 μ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD)

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches

Embedded Analog Physical Unclonable Function System to Extract Reliable and Unique Security Keys

Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal

Realization and training of an inverter-based printed neuromorphic computing system

Emerging applications in soft robotics, wearables, smart consumer products or IoT-devices benefit from soft materials, flexible substrates in conjunction with electronic functionality. Due to high production costs and conformity restrictions, rigid silicon technologies do not meet application requirements in these new domains. However, whenever signal processing becomes too comprehensive, silicon technology must be used for the high-performance computing unit. At the same time, designing everything in flexible or printed electronics using conventional digital logic is not feasible yet due to the limitations of printed technologies in terms of performance, power and integration density. We propose to rather use the strengths of neuromorphic computing architectures consisting in their homogeneous topologies, few building blocks and analog signal processing to be mapped to an inkjet-printed hardware architecture. It has remained a challenge to demonstrate non-linear elements besides weighted aggregation. We demonstrate in this work printed hardware building blocks such as inverter-based comprehensive weight representation and resistive crossbars as well as printed transistor-based activation functions. In addition, we present a learning algorithm developed to train the proposed printed NCS architecture based on specific requirements and constraints of the technology

Printed Electrodermal Activity Sensor with Optimized Filter for Stress Detection

This paper presents a tiny, flexible, and low-cost all-analog approach for measuring electrodermal activity, based on the conductance of the skin. We propose a tiny, fully-printed system on flexible substrates, which guarantees flexibility and simplifies attachment to the body, and allows for detection of high stress values in form of a binary classification. A major contribution of this paper is the design of the printed hardware, including a novel way to optimize the hardware parameters, which is done via an evolutionary algorithm