53 research outputs found
APS C++ USERβS LIBRARY
The general information about the APS algebraic programming system (terms rewriting system) is briefly described in the present article. It is justified practical necessity of creation of APS C++ Userβs Library, its conception is presented and its main functions are listed. Also it is mentioned few words about the translator APLAN-C++. \ud
ΠΠΎΡΠΎΡΠΊΠΎ ΠΎΠΏΠΈΡΠ°Π½Ρ ΠΎΠ±ΡΠΈΠ΅ ΡΠ²Π΅Π΄Π΅Π½ΠΈΡ ΠΎ ΡΠΈΡΡΠ΅ΠΌΠ΅ Π°Π»Π³Π΅Π±ΡΠ°ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΡ APS(ΡΠΈΡΡΠ΅ΠΌΠ΅ ΠΏΠ΅ΡΠ΅ΠΏΠΈΡΡΠ²Π°Π½ΠΈΡ ΡΠ΅ΡΠΌΠΎΠ²). ΠΠ±ΠΎΡΠ½ΠΎΠ²Π°Π½ΠΎ ΠΏΡΠ°ΠΊΡΠΈΡΠ΅ΡΠΊΠ°Ρ Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΠΎΡΡΡ Π² ΡΠΎΠ·Π΄Π°Π½ΠΈΠΈ Π±ΠΈΠ±Π»ΠΈΠΎΡΠ΅ΠΊΠΈ APS C++ Userβs Library, ΠΏΡΠΈΠ²Π΅Π΄Π΅Π½Π° Π΅Π΅ ΠΊΠΎΠ½ΡΠ΅ΠΏΡΠΈΡ ΠΈ ΠΏΠ΅ΡΠ΅ΡΠΈΡΠ»Π΅Π½Ρ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΡΡΠ½ΠΊΡΠΈΠΈ. Π£ΠΏΠΎΠΌΡΠ½ΡΡΠΎ ΠΎ ΡΡΠ°Π½ΡΠ»ΡΡΠΎΡΠ΅ APLAN-Π‘++. \u
Simple non-deterministic rewriting in verification
Abstract. We discuss the non-deterministic rewriting in application for engine functions of Verification of Formal Specification (VFS) system in this paper. VFS β are tools to prove properties of systems described as formal specifications (basic protocols), such as the completeness (the system behavior has a possible continuation at each of its stages) and consistency (the system behavior is deterministic at each stage), safety (something bad will never happened), or the correspondence of the specified behavior to given scenarios. Together these tools constitute a powerful environment for the formal verification of formal specifications expressed through message sequence charts
The development of interactive algorithms for the Mathematical Environment
AbstractThe Mathematical Environment which is under development at the Glushkov Institute of Cybernetics is a system of tools supporting the interactive manipulation of knowledge represented in the form of (formalized) mathematical texts. The system is implemented using a simulator for the Action Language, which has itself been developed using the algebraic programming system APS. The theoretical background of this project is the theory of interaction of agents and environments, constraint solving and the Evidence Algorithm. The main concepts underlying the project and the methodology of its development are explained in this paper in terms of the theory of interaction. The Evidence Algorithm is considered as an example of an interactive algorithm for the Mathematical Environment
Deductive verification of requirements for event-driven architecture
The current paper presents the technology of processing of requirements for systems with event-driven architecture. The technology consists of the stages of formalization, formal verification and conversion to design specifications. The formalization is the formal description of events as formal specifications called basic protocols. The consistency and completeness of basic protocols, safety properties and user-defined properties are verified. The deductive tools for dynamic and static checking are used for detection of properties violation. The method of enlargement allows reducing the complexity of proving and solving. Formal presentation of requirements allows converting them to SDL\UML specifications and generating the test suite. The technology is realized in IMS system and applied in more than 50 projects of telecommunication, networking, microprocessing and automotive systems
Satisfiability For Symbolic Verification in VRS
Π Π°ΡΡΠΌΠΎΡΡΠ΅Π½Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ Π»ΠΎΠ³ΠΈΠΊΠΈ ΠΏΠ΅ΡΠ²ΠΎΠ³ΠΎ ΠΏΠΎΡΡΠ΄ΠΊΠ° Π² ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΠΎΠΉ Π²Π΅ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ ΡΠΏΠ΅ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΉ ΡΡΠ΅Π±ΠΎΠ²Π°Π½ΠΈΠΉ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠ³ΠΎ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠ΅Π½ΠΈΡ, ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΡΠ΅ ΠΌΠΎΠ΄Π΅Π»ΠΈ ΡΠΈΡΡΠ΅ΠΌ, ΠΊΠΎΡΠΎΡΡΠ΅ Π΅ΡΡΡ ΡΡΠ°Π½Π·ΠΈΡΠΈΠΎΠ½Π½ΡΠΌΠΈ ΡΠΈΡΡΠ΅ΠΌΠ°ΠΌΠΈ Ρ ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΡΠΌΠΈ ΡΠΎΡΡΠΎΡΠ½ΠΈΡΠΌΠΈ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½Π½ΡΡ
ΡΠΎΡΠΌΡΠ»ΠΎΠΉ Π»ΠΎΠ³ΠΈΠΊΠΈ ΠΏΠ΅ΡΠ²ΠΎΠ³ΠΎ ΠΏΠΎΡΡΠ΄ΠΊΠ°. ΠΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½Ρ ΠΌΠ΅ΡΠΎΠ΄Ρ Satisfiability Modulo Theory Π²ΠΌΠ΅ΡΡΠΎ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π²ΡΠ²ΠΎΠ΄Π° Π² ΡΠΎΠΎΡΠ²Π΅ΡΡΡΠ²ΡΡΡΠ΅ΠΌ ΠΈΡΡΠΈΡΠ»Π΅Π½ΠΈΠΈ Π΄Π»Ρ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΡΡ
Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ Π² ΠΏΡΠ΅Π΄ΠΈΠΊΠ°ΡΠ½ΡΡ
ΡΡΠ°Π½ΡΡΠΎΡΠΌΠ΅ΡΠ°Ρ
.This paper demonstrates the use of the first order logic in symbolic verification of the requirement specifications of reactive software systems. We consider symbolic models of a specified system which are transition systems with symbolic states represented by formulae of the first order logic. To efficiently compute predicate transformers the Satisfiability Modulo Theory methods are used instead of the logical inference in the corresponding calculi.Π ΠΎΠ·Π³Π»ΡΠ½ΡΡΠΎ Π²ΠΈΠΊΠΎΡΠΈΡΡΠ°Π½Π½Ρ Π»ΠΎΠ³ΡΠΊΠΈ ΠΏΠ΅ΡΡΠΎΠ³ΠΎ ΠΏΠΎΡΡΠ΄ΠΊΡ Ρ ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΡΠΉ Π²Π΅ΡΠΈΡΡΠΊΠ°ΡΡΡ ΡΠΏΠ΅ΡΠΈΡΡΠΊΠ°ΡΡΠΉ Π²ΠΈΠΌΠΎΠ³ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠ½ΠΎΠ³ΠΎ Π·Π°Π±Π΅Π·ΠΏΠ΅ΡΠ΅Π½Π½Ρ, ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½Ρ ΠΌΠΎΠ΄Π΅Π»Ρ ΡΠΈΡΡΠ΅ΠΌ, ΡΠΊΡ Ρ ΡΡΠ°Π½Π·ΠΈΡΡΠΉΠ½ΠΈΠΌΠΈ ΡΠΈΡΡΠ΅ΠΌΠ°ΠΌΠΈ Π· ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΠΈΠΌΠΈ ΡΡΠ°Π½Π°ΠΌΠΈ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½ΠΈΠΌΠΈ ΡΠΎΡΠΌΡΠ»ΠΎΡ Π»ΠΎΠ³ΡΠΊΠΈ ΠΏΠ΅ΡΡΠΎΠ³ΠΎ ΠΏΠΎΡΡΠ΄ΠΊΡ. ΠΠΈΠΊΠΎΡΠΈΡΡΠ°Π½ΠΎ ΠΌΠ΅ΡΠΎΠ΄ΠΈ Satisfiability Modulo Theory Π·Π°ΠΌΡΡΡΡ Π»ΠΎΠ³ΡΡΠ½ΠΎΠ³ΠΎ Π²ΠΈΠ²ΠΎΠ΄Ρ Ρ Π²ΡΠ΄ΠΏΠΎΠ²ΡΠ΄Π½ΠΈΡ
ΡΠΈΡΠ»Π΅Π½Π½ΡΡ
Π΄Π»Ρ Π΅ΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΠ³ΠΎ ΠΎΠ±ΡΠΈΡΠ»Π΅Π½Π½Ρ Ρ ΠΏΡΠ΅Π΄ΠΈΠΊΠ°ΡΠ½ΠΈΡ
ΡΡΠ°Π½ΡΡΠΎΡΠΌΠ΅ΡΠ°Ρ
ΠΠ²ΡΠΎΠΌΠ°ΡΠΈΠ·Π°ΡΠΈΡ ΡΠΎΠ·Π΄Π°Π½ΠΈΡ Π²Π΅ΡΠΈΡΠΈΡΠΈΡΠΎΠ²Π°Π½Π½ΡΡ ΡΠ΅ΡΡΠΎΠ²ΡΡ ΡΡΠ΅Π½Π°ΡΠΈΠ΅Π² Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ Π³ΠΈΠ΄ΠΎΠ²
This paper presents an overview of technology of the automated generation of test scenarios based on guides. The usage of this technology can significantly improve the quality of the developed program products. In order to ground the technology creation, the main problems that occur during the development and testing of the large industrial systems, are described, as well as the methodologies of software verification on conformity to product requirements. The potentialities of tools for automatic and semi-automatic generation of a test suite by using a formal model in UCM notation are demonstrated, as well as tools for verification and automation of testing.Π Π΄Π°Π½Π½ΠΎΠΉ ΡΠ°Π±ΠΎΡΠ΅ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½ ΠΎΠ±Π·ΠΎΡ ΡΠ΅Ρ
Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·ΠΈΡΠΎΠ²Π°Π½Π½ΠΎΠΉ Π³Π΅Π½Π΅ΡΠ°ΡΠΈΠΈ ΡΠ΅ΡΡΠΎΠ²ΡΡ
ΡΡΠ΅Π½Π°ΡΠΈΠ΅Π² Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ Π³ΠΈΠ΄ΠΎΠ², ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ ΠΊΠΎΡΠΎΡΠΎΠΉ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΡΡΡΠ΅ΡΡΠ²Π΅Π½Π½ΠΎ ΠΏΠΎΠ²ΡΡΠΈΡΡ ΠΊΠ°ΡΠ΅ΡΡΠ²ΠΎ ΡΠ°Π·ΡΠ°Π±Π°ΡΡΠ²Π°Π΅ΠΌΠΎΠ³ΠΎ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠ³ΠΎ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠ΅Π½ΠΈΡ. Π ΠΊΠ°ΡΠ΅ΡΡΠ²Π΅ ΠΎΠ±ΠΎΡΠ½ΠΎΠ²Π°Π½ΠΈΡ ΡΠΎΠ·Π΄Π°Π½ΠΈΡ ΡΠ΅Ρ
Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ ΠΎΠΏΠΈΡΠ°Π½Ρ ΠΎΡΠ½ΠΎΠ²Π½ΡΠ΅ ΠΏΡΠΎΠ±Π»Π΅ΠΌΡ, Π²ΠΎΠ·Π½ΠΈΠΊΠ°ΡΡΠΈΠ΅ ΠΏΡΠΈ ΡΠ°Π·ΡΠ°Π±ΠΎΡΠΊΠ΅ ΠΈ ΡΠ΅ΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΠΈ ΠΊΡΡΠΏΠ½ΡΡ
ΠΏΡΠΎΠΌΡΡΠ»Π΅Π½Π½ΡΡ
ΡΠΈΡΡΠ΅ΠΌ, ΠΈ ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½Ρ ΠΌΠ΅ΡΠΎΠ΄ΠΈΠΊΠΈ ΠΏΡΠΎΠ²Π΅ΡΠΊΠΈ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠ³ΠΎ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠ΅Π½ΠΈΡ Π½Π° ΡΠΎΠΎΡΠ²Π΅ΡΡΡΠ²ΠΈΠ΅ ΡΡΠ΅Π±ΠΎΠ²Π°Π½ΠΈΡΠΌ. ΠΡΠΎΠ΄Π΅ΠΌΠΎΠ½ΡΡΡΠΈΡΠΎΠ²Π°Π½Ρ Π²ΠΎΠ·ΠΌΠΎΠΆΠ½ΠΎΡΡΠΈ ΠΈΠ½ΡΡΡΡΠΌΠ΅Π½ΡΠ°Π»ΡΠ½ΡΡ
ΡΡΠ΅Π΄ΡΡΠ² ΠΏΠΎ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠΉ ΠΈ ΠΏΠΎΠ»ΡΠ°Π²ΡΠΎΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠΉ Π³Π΅Π½Π΅ΡΠ°ΡΠΈΠΈ ΡΠ΅ΡΡΠΎΠ²ΠΎΠ³ΠΎ Π½Π°Π±ΠΎΡΠ° Ρ ΠΈΡ- ΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ ΡΠΎΡΠΌΠ°Π»ΡΠ½ΠΎΠΉ ΠΌΠΎΠ΄Π΅Π»ΠΈ, ΡΠΎΠ·Π΄Π°Π½Π½ΠΎΠΉ Π½Π° ΡΠ·ΡΠΊΠ΅ UCM, ΠΈ ΡΡΠ΅Π΄ΡΡΠ² Π²Π΅ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ ΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·Π°ΡΠΈΠΈ ΡΠ΅ΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ
ΠΠ½ΠΊΡΠ΅ΠΌΠ΅Π½ΡΠ°Π»ΡΠ½ΡΠΉ ΠΏΠΎΠ΄Ρ ΠΎΠ΄ ΠΊ ΡΠ΅Ρ Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ ΡΠΎΠ·Π΄Π°Π½ΠΈΡ ΡΠ΅ΡΡΠΎΠ² Π΄Π»Ρ ΠΈΠ½Π΄ΡΡΡΡΠΈΠ°Π»ΡΠ½ΡΡ ΠΏΡΠΎΠ΅ΠΊΡΠΎΠ²
The paper presents an approach to effort reduction in developing test suites for industrial software products based on the incremental technology. The main problems to be solved by the incremental technology are full automation design of test scenarios and significant reducing of test explosion. The proposed approach provides solutions to the mentioned problems through joint co-working of a designer and a customer, through the integration of symbolic verification with the automatic generation of test suites; through the usage of an efficient technology with the toolset VRS/TAT.Π‘ΡΠ°ΡΡΡ ΠΏΠΎΡΠ²ΡΡΠ΅Π½Π° ΠΎΠΏΠΈΡΠ°Π½ΠΈΡ ΡΠ΅Ρ
Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ, ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡΡΠ΅ΠΉ ΡΠΎΠΊΡΠ°ΡΠΈΡΡ ΡΡΡΠ΄ΠΎΠ·Π°ΡΡΠ°ΡΡ Π½Π° ΡΠΎΠ·Π΄Π°Π½ΠΈΠ΅ ΡΠ΅ΡΡΠΎΠ² Π΄Π»Ρ ΠΏΡΠΎΠΌΡΡΠ»Π΅Π½Π½ΡΡ
ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ
ΠΏΡΠΎΠ΅ΠΊΡΠΎΠ², Π·Π° ΡΡΠ΅Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΡ ΠΈΠ½ΠΊΡΠ΅ΠΌΠ΅Π½ΡΠ°Π»ΡΠ½ΠΎΠ³ΠΎ ΠΏΠΎΠ΄Ρ
ΠΎΠ΄Π°. ΠΡΠ½ΠΎΠ²Π½Π°Ρ ΠΏΡΠΎΠ±Π»Π΅ΠΌΠ°, ΡΠ΅ΡΠ΅Π½Π½Π°Ρ Π² Π΄Π°Π½Π½ΠΎΠΉ ΡΠ°Π±ΠΎΡΠ΅, ΡΠ²ΡΠ·Π°Π½Π° Ρ ΠΏΠΎΠ»Π½ΠΎΠΉ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·Π°ΡΠΈΠ΅ΠΉ ΡΠ°Π·Ρ Π΄ΠΈΠ·Π°ΠΉΠ½Π° ΡΠ΅ΡΡΠΎΠ²ΡΡ
ΡΡΠ΅Π½Π°ΡΠΈΠ΅Π² ΠΈ ΡΠΎΠΊΡΠ°ΡΠ΅Π½ΠΈΠ΅ΠΌ ΠΊΠΎΠ»ΠΈΡΠ΅ΡΡΠ²Π° ΡΠ΅ΡΡΠΎΠ², Π½Π΅ΠΎΠ±Ρ
ΠΎΠ΄ΠΈΠΌΡΡ
Π΄Π»Ρ ΠΎΠ±Π΅ΡΠΏΠ΅ΡΠ΅Π½ΠΈΡ ΠΊΠ°ΡΠ΅ΡΡΠ²Π° ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΠΎΠ³ΠΎ ΠΏΡΠΎΠ΄ΡΠΊΡΠ°. ΠΡΠ΅Π΄Π»Π°Π³Π°Π΅ΠΌΠ°Ρ Π² ΡΠ°Π±ΠΎΡΠ΅ ΡΠ΅Ρ
Π½ΠΎΠ»ΠΎΠ³ΠΈΡ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΡΠ΅ΡΠΈΡΡ ΡΠΊΠ°Π·Π°Π½Π½ΡΠ΅ ΠΏΡΠΎΠ±Π»Π΅ΠΌΡ Π·Π° ΡΡΠ΅Ρ ΡΠΎΠ²ΠΌΠ΅ΡΡΠ½ΠΎΠΉ ΡΠ°Π±ΠΎΡΡ Π΄ΠΈΠ·Π°ΠΉΠ½Π΅ΡΠ° ΡΠ΅ΡΡΠΎΠ²ΡΡ
Π½Π°Π±ΠΎΡΠΎΠ² ΠΈ Π·Π°ΠΊΠ°Π·ΡΠΈΠΊΠ° Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ ΡΠΎΡΠΌΠ°Π»ΡΠ½ΡΡ
ΠΌΠΎΠ΄Π΅Π»Π΅ΠΉ, ΠΌΠ΅ΡΠΎΠ΄ΠΎΠ² ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΠΎΠΉ Π²Π΅ΡΠΈΡΠΈΠΊΠ°ΡΠΈΠΈ ΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΎΠΉ Π³Π΅Π½Π΅ΡΠ°ΡΠΈΠΈ ΡΠ΅ΡΡΠΎΠ²ΡΡ
Π½Π°Π±ΠΎΡΠΎΠ² Π½Π° Π±Π°Π·Π΅ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΡ ΠΈΠ½ΡΡΡΡΠΌΠ΅Π½ΡΠ°ΡΠΈΡ VRS/TAT
ΠΠΎΠ΄Ρ ΠΎΠ΄ ΠΊ ΠΊΠΎΠ½ΠΊΡΠ΅ΡΠΈΠ·Π°ΡΠΈΠΈ ΡΠ΅ΡΡΠΎΠ²ΡΡ ΡΡΠ΅Π½Π°ΡΠΈΠ΅Π² Π² ΡΠ°ΠΌΠΊΠ°Ρ ΡΠ΅Ρ Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·Π°ΡΠΈΠΈ ΡΠ΅ΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΏΡΠΎΠΌΡΡΠ»Π΅Π½Π½ΡΡ ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ ΠΏΡΠΎΠ΅ΠΊΡΠΎΠ²
In this paper we propose an approach to efficient automating test technology for industrial software projects, that uses a formal model of the system, automatically performs a symbolic verification, generation and concretization of the symbolic traces, the generation of test suites for concretized traces, and also includes tools for analysis of the testing results, allowing users to automate the full cycle of testing. Particular emphasis is placed on the presentation of the algorithm concretization and setting of test scenarios.ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½ ΠΏΠΎΠ΄Ρ
ΠΎΠ΄ ΠΊ ΡΠΎΠ·Π΄Π°Π½ΠΈΡ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΠΉ ΡΠ΅Ρ
Π½ΠΎΠ»ΠΎΠ³ΠΈΠΈ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·Π°ΡΠΈΠΈ ΡΠ΅ΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΏΡΠΎΠΌΡΡΠ»Π΅Π½Π½ΡΡ
ΠΏΡΠΎΠ³ΡΠ°ΠΌΠΌΠ½ΡΡ
ΠΏΡΠΎΠ΅ΠΊΡΠΎΠ², ΠΊΠΎΡΠΎΡΡΠΉ ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΠ΅Ρ ΡΠΎΡΠΌΠ°Π»ΡΠ½ΡΡ ΠΌΠΎΠ΄Π΅Π»Ρ ΡΠΈΡΡΠ΅ΠΌΡ, Π²ΡΠΏΠΎΠ»Π½ΡΠ΅Ρ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΡΠ΅ΡΠΊΠΈ ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΡΡ Π²Π΅ΡΠΈΡΠΈΠΊΠ°ΡΠΈΡ, Π³Π΅Π½Π΅ΡΠ°ΡΠΈΡ ΠΈ ΠΊΠΎΠ½ΠΊΡΠ΅ΡΠΈΠ·Π°ΡΠΈΡ ΡΠΈΠΌΠ²ΠΎΠ»ΡΠ½ΡΡ
ΡΡΠ°ΡΡ, Π³Π΅Π½Π΅ΡΠ°ΡΠΈΡ ΡΠ΅ΡΡΠΎΠ²ΡΡ
Π½Π°Π±ΠΎΡΠΎΠ² ΠΏΠΎ ΠΊΠΎΠ½ΠΊΡΠ΅ΡΠΈΠ·ΠΈΡΠΎΠ²Π°Π½Π½ΡΠΌ ΡΡΠ°ΡΡΠ°ΠΌ, Π° ΡΠ°ΠΊΠΆΠ΅ Π²ΠΊΠ»ΡΡΠ°Π΅Ρ ΡΡΠ΅Π΄ΡΡΠ²Π° Π°Π½Π°Π»ΠΈΠ·Π° ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΠΎΠ² ΠΈΡΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ ΡΠ΅ΡΡΠΎΠ², ΠΏΠΎΠ·Π²ΠΎΠ»ΡΡ Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠ·ΠΈΡΠΎΠ²Π°ΡΡ ΠΏΠΎΠ»Π½ΡΠΉ ΡΠΈΠΊΠ» ΡΠ΅ΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ. ΠΡΠΎΠ±ΡΠΉ Π°ΠΊΡΠ΅Π½Ρ ΡΠ΄Π΅Π»Π°Π½ Π½Π° ΠΈΠ·Π»ΠΎΠΆΠ΅Π½ΠΈΠΈ Π°Π»Π³ΠΎΡΠΈΡΠΌΠ° ΠΊΠΎΠ½ΠΊΡΠ΅ΡΠΈΠ·Π°ΡΠΈΠΈ ΠΈ Π½Π°ΡΡΡΠΎΠΉΠΊΠΈ ΡΠ΅ΡΡΠΎΠ²ΡΡ
ΡΡΠ΅Π½Π°ΡΠΈΠ΅Π²
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