16 research outputs found
μ¬λ¬ κ°μ§ λ©λͺ¨λ¦¬ μμμμμ RTN νΉμ± λΆμ (SRAM, DRAM, Flash)
νμλ
Όλ¬Έ(λ°μ¬)--μμΈλνκ΅ λνμ :곡과λν μ κΈ°Β·μ»΄ν¨ν°κ³΅νλΆ,2019. 8. μ νμ² .λ³Έ λ
Όλ¬Έμμλ μμ μ‘μμ μ’
λ₯ μ€ νλμΈ Random Telegraph Noise (RTN) ν¨κ³Όλ₯Ό μ¬λ¬κ°μ§ λ©λͺ¨λ¦¬ μμ (SRAM, DRAM, Flash)μμ λΆμνμλ€. κΈ°λ³Έμ μΌλ‘, RTNμ μμμ νΈλ©μ μκ°μ λ°λ₯Έ μ μμ ν¬ν/λ°©μΆ νμμ μν΄μ λνλκ³ , μμμ μ λ₯ λ° λ¬Έν± μ μμ λ³νλ₯Ό μΌκΈ°νλ€. μ΄λ¬ν νμμ λ©λͺ¨λ¦¬ μμμμ μ¬λ¬κ°μ§ μ λ’°μ± λ¬Έμ μ μμΈμΌλ‘ μμ©νλ©° νΉν, SRAMμμμ λ
Έμ΄μ¦ λ§μ§ κ°μ, DRAMμμμ VRT νμ κ·Έλ¦¬κ³ Flashμμμ λ¬Έν± μ μ λ³λμ μμΈμΌλ‘ μμ©νλ€.
6κ°μ νΈλμ§μ€ν°λ‘ μ΄λ£¨μ΄μ§ SRAMμ Read λμμμμ λ²ν°νλΌμ΄ 곑μ μμ μ΅λ μ μ¬κ°νμ ν¬κΈ°λ‘ λ
Έμ΄μ¦ λ§μ§μ΄ μ μλλ€. μ΄λ¬ν λ
Έμ΄μ¦ λ§μ§μ Pull UP (PU)μ Pull Down (PD)μ Subthreshold Swing λ° VT mismatch, κ·Έλ¦¬κ³ Pass Gate (PG)μ PDμ μ ν μ°¨μ΄μ μν΄μ κ²°μ λλ€. SRAM μμμ μ΄λ ν μ‘°ν©μΌλ‘ RTN Trapμ΄ μμ λ, VT mismatch λ° μ ν μ°¨μ΄κ° μ μΌ μ»€μ Έμ λ
Έμ΄μ¦ λ§μ§μ΄ μ΅λλ‘ κ°μνλμ§λ₯Ό λΆμνμκ³ μΆκ°μ μΌλ‘, μ¬λ¬κ°μ§ Variability sourceλ€κ³Ό ν¨κ» RTN ν¨κ³Όλ₯Ό λΆμνμλ€.
DRAM cellμ retention timeμ κ²μ΄νΈμ λλ μΈμ μ€λ²λ© μμμμ λ°μνλ Gate Induced Drain Leakage(GIDL) μ λ₯μ μν₯μ λ°λλ€. μ΄ GIDL μ λ₯λ RTN νμμ μν΄μ μκ°μ λ°λΌ κ°μ΄ λ°λλ©°, DRAM cellμ variable retention time (VRT) νμμ μμΈμ΄ λλ€. VRT νμμ μ νν μ΄ν΄νκΈ° μν΄μ GIDL μ λ₯ RTNμ μμΈμ΄ λλ νΈλ©μ λν 물리μ νΉμ± μ΄ν΄κ° λ°λμ μ΄λ£¨μ΄μ ΈμΌ νκ³ , νμ¬κΉμ§ λ§μ κ·Έλ£Ήμμ μ°κ΅¬λ₯Ό μ§ννμλ€. νμ§λ§, μ¬λ¬κ°μ§ λ
Όλ¬Έμμ μ κ³μ ν¬κΈ°λ₯Ό κ³ λ €νμ§ λͺ»νκ³ μλͺ»λ μμμ μ¬μ©νμ¬ νΈλ© νΉμ±μ λΆμνμλ€. λ³Έ λ
Όλ¬Έμμλ μ κ³μ ν¬κΈ°λ₯Ό κ³ λ €νμ¬ λ μ ννκ² νΈλ©μ νΉμ±μ λΆμνλ μ°κ΅¬λ₯Ό μ§ννμκ³ , μ΄λ¬ν μ°κ΅¬λ DRAMμ VRTνμμ μ΄ν΄νλλ° ν° λμμ΄ λ κ²μ΄λ€.
3D NANDλ μ±λ λ¬Όμ§μ΄ ν΄λ¦¬μ€λ¦¬μ½μΌλ‘ νμ±λμ΄ μμ΄, μμμ μΌλ‘ νμ±λλ Grain Boundary Trap (GBT)μ μν μμμ μ λ’°μ± λ¬Έμ κ° ν° μ΄μμ΄λ€. νΉν μ±λμ μ λ₯κ° κ· μΌνκ² νλ₯΄μ§ μκ³ , κ³μνμ¬ μ¦κ°νλ λ¨ μ λ° μ€μ΄λλ μμ ꡬ쑰μμ RTN ν¨κ³Όκ° λμ± λ μ€μν μ λ’°μ± λ¬Έμ κ° λκ³ μλ€. λ³Έ λ
Όλ¬Έμμλ μ¬λ¬κ°μ§ μν©(RTN νΈλ© μμΉ, μ¨λ, μμ μΆμν, GBT λ°λ λ±)μμμ RTN ν¨κ³Όλ₯Ό λΆμν¨μΌλ‘μ¨ μμΌλ‘ 3D NANDμ VT λ³λμμμ RTN μν₯λ ₯μ μμΈ‘νλλ° λμμ μ€λ€.In this thesis, Random Telegraph Noise (RTN) effect, which is one kind of device noise, is analyzed in various memory devices (SRAM, DRAM, Flash). Basically, RTN is caused by trapping/de-trapping phenomenon of electron in the trap of the device over time, causing a change in current and threshold voltage of the device. This phenomenon causes various reliability problems in the memory device. In particular, it reduces noise margin in SRAM, causes the Variable Retention Time (VRT) phenomenon in DRAM, and changes the threshold voltage in Flash.
In a six-transistor of SRAM, the noise margin is defined as the maximum square size in the butterfly curve in Read operation. This noise margin is determined by subthreshold swing and VT mismatch of Pull UP (PU) and Pull Down (PD), and resistance difference between Pass Gate (PG) and PD. In the case of RTN trap in any combination of SRAM devices, we analyzed whether the VT mismatch and the resistance difference were the largest and the noise margin was reduced to the maximum. In addition, we analyzed the RTN effect with various variability sources.
The retention time of the DRAM cell is affected by the gate induced drain leakage (GIDL) current generated in the overlap region of the gate and the drain. This GIDL current changes with time due to the RTN phenomenon, which causes the VRT of the DRAM cell. In order to understand the VRT phenomenon accurately, understanding the physical characteristics of the trap that causes the GIDL RTN must be understood, and researches have been carried out in many groups. However, in various papers, it could not consider the electric field and analyzed the trap characteristics using the wrong formula. In this paper, we have studied the characteristics of the traps more accurately by considering the electric field enhancement factor. This study will be helpful for understanding the VRT phenomenon of DRAM.
In the 3D NAND, since the channel material is formed of polysilicon, the reliability problem of the device due to arbitrarily formed Grain Boundary Trap (GBT) is a big issue. Especially, because the channel current does not flow uniformly, the RTN effect becomes more important reliability problem in the continuously decreasing device structure. In this thesis, we analyze the effect of RTN on various situations (RTN trap location, temperature, device miniaturization, GBT density, etc.) and help to predict RTN effect on VT fluctuation in macaroni-type 3D NAND Flash memory.CONTENTS
Abstract i
Chapter 1. Introduction
1.1. What is Random Telegraph Noise? 1
1.2. Impact of RTN in memory devices 3
Chapter 2. Impact of RTN in Bulk FinFET on the Stability of SRAM Cells [SRAM]
2.1. Introduction 6
2.2. Results and Discussion 7
2.3. Summary 13
Chapter 3. Extraction of Distance between Interface Trap and Oxide Trap from RTN in Gate-Induced Drain Leakage [DRAM]
3.1. Introduction 14
3.2. Results and Discussion 15
3.3. Summary 27
Chapter 4. Prediction of RTN Effect on VT Fluctuation in Macaroni-type 3D NAND Flash Memories [Flash]
4.1. Introduction 29
4.2 Simulation Structure and Methodology 32
4.3. Results and Discussion 35
4.4. Summary 47
Chapter 5. Conclusion 50
Appendix A. Improving BSIM Flicker Noise Model
A.1. Introduction 52
A.2. Advanced Flicker Noise Model 53
A.3. Results and Discussion 56
A.4. Conclusion 64
Abstract in Korean 65
List of Publications 68Docto
Fusarium sp. BYA-1μ΄ μμ±νλ μΈκ°μ νμ§κ· μ± νμλ¬Όμ§μ λΆλ¦¬μ λμ
Thesis (master`s)--μμΈλνκ΅ λνμ :λμλ¬Όνκ³Ό μλ¬Όλ³λ¦¬νμ 곡,1996.Maste
μ₯μμμ 보리μ λν Fusarium isolatesμ trichothecene μμ±λ₯κ³Ό λ³μμ±
Thesis (master`s)--μμΈλνκ΅ λνμ :λμλ¬Όνκ³Ό μλ¬Όλ³λ¦¬νμ 곡,1997.Maste