단일 및 다중 행 직접회로 레이아웃 알고리즘

학위논문(박사) - 한국과학기술원 : 전기및 전자공학과, 1992.2, [ iii, 83 p. ]Designers of CMOS VLSI circuits can take advantage of logic modules to achieve better performance and better turn-around time. For synthesizing the logic modules automatically, two problems are to be solved; one is the problem of minimizing the widths of logic modules, and the other is the problem of determining the heights of logic modules, that is, minimizing the sum of all row heights in standard cell layouts satisfying the delay time and minimum dimension constraints, both of which are known as NP-complete. In this thesis, three algorithms are devised for solving these two problems. Our first algorithm solves the former problem, where the problem is converted to that of decomposing the transistor connection graph into a minimum number of subgraphs, each having a pair of Euler trails with the same sequence of input labels on the N-graph and P-graph, which are portions of the graph corresponding to NMOS and PMOS parts, respectively, and some heuristics are used to yield a nearly minimum number of Euler trails from the trail representation formula which represents the given logic function. Subtrail merging is done through a list processing scheme where the pair of trails which results in the lowest cost is successively merged from all candidate merge pairs sutil no further trail merging and further reduction of number of subgraphs are possible. A salient feature of our proposed algorithm is that virtually all permutation of the subtrails are considered within the time complexity of $O(n^3)$, which has to be contrasted with the time complexity of $O(n^n)$ in [2] and [3] considering all permutations within each subtrail. Our second algorithm also solves the former problem, where the problem is converted to that of determining the covering sets for each of the given Boolean logic expression and merging all the covering sets in all possible ways to find the optimum solution being characterized by the minimum number of dual trails, corresponding to the minimum numb...한국과학기술원 : 전기및 전자공학과