736 research outputs found

    5KW pulse width modulated static inverter

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    Design verification tests for logic and low level circuits, and preliminary single-phase breadboard of pulse width modulated static inverte

    Efficiency analysis of wide band-gap semiconductors for two-level and three-level power converters

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    © 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Power devices based on wide band-gap materials are emerging as alternatives to silicon-based devices. These new devices allow designing and building converters with fewer power losses, and are thus more highly efficient than traditional power converters. Among the wide band-gap materials in use, silicon carbide (SiC) and gallium nitride (GaN) devices are the most promising because of their excellent properties and commercial availability. This paper compares the losses produced in two-level and three-level power converters that use the aforementioned technologies. In addition, we assess the impact on the converter performance caused by the modulation technique. Simulation results under various operating points are reported and compared.Peer ReviewedPostprint (author's final draft

    Soft switching techniques for multilevel inverters

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    Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia Elétrica

    A Component-Reduced Zero-Voltage Switching Three-Level DC-DC Converter

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    Control And Topology Improvements In Half-bridge Dc-dc Converters

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    Efficiency and transient response are two key requirements for DC-DC converters. Topology and control are two key topics in this dissertation. A variety of techniques for DC-DC converter performance improvement are presented in this work. Focusing on the efficiency issue, a variety of clamping techniques including both active and passive methods are presented after the ringing issues in DC-DC converters are investigated. By presenting the clamping techniques, a big variety of energy management concepts are introduced. The active bridge-capacitor tank clamping and FET-diode-capacitor tank clamping are close ideas, which transfer the leakage inductor energy to clamping capacitor to prevent oscillation between leakage inductor and junction capacitor of MOSFETs. The two-FET-clamping tank employs two MOSFETs to freewheeling the leakage current when the main MOSFETs of the half-bridge are both off. Driving voltage variation on the secondary side Synchronous Rectifier (SR) MOSFETs in self-driven circuit due to input voltage variation in bus converter applications is also investigated. One solution with a variety of derivations is proposed using zerner-capacitor combination to clamping the voltage while maintaining reasonable power losses. Another efficiency improvement idea comes from phase-shift concept in DC-DC converters. By employing phase-shift scheme, the primary side and the secondary side two MOSFETs have complementary driving signals respectively, which allow the MOSFET to be turned on with Zero Voltage Switching (ZVS). Simulation verified the feasibility of the proposed phase-shifted DC-DC converter. From the control scheme point of view, a novel peak current mode control concept for half-bridge topologies is presented. Aiming at compensating the imbalanced voltage due to peak current mode control in symmetric half-bridge topologies, an additional voltage compensation loop is used to bring the half-bridge capacitor voltage back to balance. In the proposed solutions, one scheme is applied on symmetric half-bridge topology and the other one is applied on Duty-cycle-shifted (DCS) half-bridge topology. Both schemes employ simple circuitry and are suitable for integration. Loop stability issues are also investigated in this work. Modeling work shows the uncompensated half-bridge topology cannot be stabilized under all conditions and the additional compensation loop helps to prevent the voltage imbalance effectively
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