2D-TCAD Simulation on Retention Time of Z2FET for DRAM Application

Traditional memory devices are facing more challenges due to continuous down-scaling. 6T-SRAM suffers from variability [1-2] and reliability [3-4] issues, which introduce cell stability problems. DRAM cells with one transistor, one capacitor (1T1C) struggle to maintain refresh time [5-6]. Efforts have been made to find new memory solutions, such as one transistor (1T) solutions [7-9]. Floating body based memory structures are among the potential candidates, but impact ionization or band-to-band tunnelling (B2BT) limits their refresh time [10]. A recently proposed zero impact ionization and zero subthreshold swing device named Z2FET [9, 11-12] has been demonstrated and is a promising candidate for 1T DRAM memory cell due to technology advantages such as CMOS technology compatibility, novel capacitor-less structure and sharp switching characteristics. In the Z2FET memory operation, refresh frequency is determined by data retention time. Previous research [11-12] is lacking systematic simulation analysis and understanding on the underlying mechanisms. In this paper, we propose a new simulation methodology to accurately extract retention time in Z2FET devices and understand its dependency on applied biases, temperatures and relevant physical mechanisms. Since the stored ‘1’ state in Z2FET is an equilibrium state [9, 11-12] and there is no need to refresh, we will concentrate on state ‘0’ retention. Two types of ‘0’ retention time: HOLD ‘0’ and READ ‘0’ retention time will be discussed separately

Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells

Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FD SOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.H2020 REMINDER European project (grant agreementNo 687931) and TEC2014-59730 are thanked for financialsupport

Simulation Based DC and Dynamic Behaviour Characterization of Z2FET

This work presents a TCAD investigation of the operation of a Z2FET device for memory application, where the TCAD model is well calibrated to experimental hysteresis curves. The DC operation of the Z2FET has been analyzed for 4 cases, based on the permutations of the front and back gate biases, to identify and compare different modes of operation. The memory mode of operation is under the “Thyristor” like scenario with positive and negative biases applied to the front and back gates respectively. The dynamic property of Z2FET as a memory device is shown and its operation mechanism is described

On the Low-Frequency Noise Characterization of Z2-FET Devices

This paper addresses the low-frequency noise characterization of Z2-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed.This work was supported in part by the European REMINDER 687931 Grant, in part by the Consejeria de Economia, Conocimiento, Empresas y Universidad de la Junta de Andalucia and European Regional Development Fund (ERDF), under Grant SOMM17/6109/ UGR, and in part by the TEC2017-89800-R Project

Simulation Perspectives of Sub-1V Single-Supply Z2-FET 1T-DRAM Cells for Low-Power

With the upcoming Internet of Things (IoT), low-power devices are becoming mainstream these days. The need for memory elements able to operate at reduced biasing conditions is therefore of utmost importance. In this paper, one of the most promising capacitor-less dynamic RAM cell, the Z2-FET (zero subthreshold swings, zero impact ionization field-effect transistor), is analyzed through advanced numerical simulations to study its sub-1V operation capabilities. SiGe compounds and tuned workfunction are selected to further reduce the operating voltage to limit energy consumption. The results demonstrate functional SiGe cells with up to 75% energy reduction with respect to identical Si cells.This work was supported in part by the H2020 REMINDER European under Grant 687931, and in part by the Spanish under Project TEC2017-89800-R and Project IJCI-2016-27711

Reliability Study of Thin-Oxide Zero-Ionization, Zero-Swing FET 1T-DRAM Memory Cell

The experimental time-dependent dielectric breakdown and ON voltage reliability of advanced FD-SOI Z2-FET memory cells are characterized for the first time. The front-gate stress time is shown to significantly modulate the ON voltage and, hence, the memory window. The Weibull slope, β, indicating the device variability to breakdown, and the time to soft breakdown, α, present different trends depending on the cell geometry. This fact highlights the tradeoff between variability and reliability to account for in Z2-FET designs.H2020 REMINDER project (grant agreement No 687931) and TEC2017-89800-R are thanked for financial support

Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM

This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). DOI: 10.1109/TED.2017.2751141(c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works."The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions

Dispositifs innovants à pente sous le seuil abrupte (du TEFT au Z -FET)

Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d effet tunnel. Un modèle analytique combinantl effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z -FET estégalement démontrée sans nécessité de rafraichissement de l information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/ m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte.This thesis is dedicated to studying sharp switching devices, including the tunneling field-effect-transistor(TFET) and a new feedback device we have named the Z2-FET, for low power logic and memory applicationscompatible with modern silicon technology. We have extensively investigated TFETs with various gate oxides,channel materials and structures, fabricated on fully-depleted silicon-on-insulator (FD-SOI) substrates.Low-frequency noise (LFN) measurements were performed on TFETs, showing the dominance of randomtelegraphy signal (RTS) noise, which reveals the tunneling mechanism. An analytical TFET model combiningtunneling and channel transport has been developed, showing agreement with the experimental and simulationresults.We also conceived and demonstrated a new device named the Z2-FET (for zero subthreshold swing andzero impact ionization), which exhibits extremely sharp switching with subthreshold swing SS 4.10-3 A/ mand SS < 60 mV/dec over 7 decades of current, outperforming all silicon-compatible TFETs reported to date.The thesis concludes with future research directions in the sharp-switching device arena.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

3D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z 2 -FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (D it ) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation.H2020 REMINDER European (grant agreement No 687931) and Spanish National TEC2017-89800-R and PCIN-2015-146 projects are acknowledged for financial support

InGaAs Capacitor-Less DRAM Cells TCAD Demonstration

2D numerical TCAD simulations are used to infer the behavior of III-V capacitor-less dynamic RAM (DRAM) cells. In particular, indium gallium arsenide on insulator technology is selected to verify the viability of III-V meta-stable-dip RAM cells. The cell performance dependence on several parameters (such as the back-gate voltage, semiconductor thickness, indium/gallium mole fraction or interface traps) and simulation models (like ballisticity or spatial quantum confinement) is analyzed and commented. Functional cells are presented and compared with analogous silicon 1T-DRAM memories to highlight the advantages and drawbacks.This work was supported by H2020 REMINDER European under Grant 687931, and in part by the Spanish National Projects under Grant TEC2014-59730 and Grant PCIN-2015-146