Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin Sean; Committee Member: Mukhopadhyay, Saiba

A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results

Dependable Embedded Systems

This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

A Scalable Workflow for a Configurable Neuromorphic Platform

This thesis establishes a scalable multi-user workflow for the operation of a highly configurable, large-scale neuromorphic hardware platform. The resulting software framework provides unified low-level as well as parallel high-level access. The latter is realized by an efficient abstract neural network description library, an automated translation of networks into hardware specific configurations and an experiment server infrastructure responsible for scheduling and executing experiments. Scalability, manual guidance and a broad support for handling hardware imper- fections render the model translation process suitable for large networks as well as large-scale neuromorphic systems. Networks with local connectivity, random networks and cortical column models are explored to study the topological aptitude of the neuromorphic platform and to benchmark the workflow. Depending on the model, performance improvements of more than two orders of magnitude have been achieved over a previous implementation. Additionally, an automated defect assessment for hardware synapses is introduced, indicating that most synapses are available for model emulation. In a second study, a tempotron-based hardware liquid state machine has been developed and applied to different tasks, including a memory challenge and digit recognition. The trained tempotron inherently compensates for fixed pattern variations making the setup suitable for analog neuromorphic hardware. The achieved performance is comparable to reference software simulations

Characterisation and modelling of Random Telegraph Noise in nanometre devices

The power consumption of digital circuits is proportional to the square of operation voltage and the demand for low power circuits reduces the operation voltage towards the threshold of MOSFETs. A weak voltage signal makes circuits vulnerable to noise and the optimization of circuit design requires an accurate noise model. RTN is the dominant noise for modern CMOS technologies. This research focuses on the instability induced by Random Telegraph Noise (RTN) in nano-devices for low power applications, such as the Internet of Things (IoT). RTN is a stochastic noise that can be observed in the drain/gate current of a device when traps capture and emit electrons or holes. The impact of RTN instabilities in devices has been widely investigated. Although progress has been made, the understanding of RTN instabilities remains incomplete and many issues are unresolved. This work focuses on developing a statistical model for characterising, modelling and analysing of the impact of RTN on MOSFET performance, as well as to study the prediction for long-term RTN impact on real circuits. As transistor sizes are downscaled, a single trapped charge has a larger impact and RTN becomes increasingly important. To optimize circuit design, one needs to assess the impact of RTN on circuits, which can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs has been too limited to establish their statistical distribution reliably. In particular, the time window used has often been small, e.g. 10 sec or less, so that there is little data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The first contribution of this work is three-fold: to provide long-term RTN data and use it to test the CET distributions proposed by early works; to propose a methodology for characterising the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long-term prediction capability of a CET distribution beyond the time window used for its extraction. On the statistical distributions of RTN amplitude, three different distributions were proposed by early works: Lognormal, Exponential, and Gumbel distributions. They give substantially different RTN predictions and agreement has not been reached on which distribution should be used, calling the modelling accuracy into question. The second contribution of this work is to assess the accuracy of these three distributions and to explore other distributions for better accuracy. A novel criterion has been proposed for selecting distributions, which requires a monotonic reduction of modelling errors with increasing number of traps. The three existing distributions do not meet this criterion and thirteen other distributions are explored. It is found that the Generalized Extreme Value (GEV) distribution has the lowest error and meets the new criterion. Moreover, to reduce modelling errors, early works used bimodal Lognormal and Exponential distributions, which have more fitting parameters. Their errors, however, are still higher than those of the monomodal GEV distribution. GEV has a long distribution tail and predicts substantially worse RTN impact. The project highlights the uncertainty in predicting the RTN distribution tail by different statistical models. The last contribution of the project is studying the impact of different gate biases on RTN distributions. At two different gate voltage conditions: one close to threshold voltage |Vth| and the other under operating conditions, it is found that the RTN amplitude follows different distributions. At operating voltage condition, Lognormal distribution has the lowest error for RTN amplitude distribution in comparison with other distributions. The amplitude distribution at close to |Vth| has a longer tail compared with the distribution tail at operating voltage. However, RTN capture/emission time distribution is not impacted by gate bias and follows Log-uniform distribution

High Efficiency Microwave Amplifiers and SiC Varactors Optimized for Dynamic Load Modulation

The increasing use of mobile networks as the main source of internet connectivity is creating challenges in the infrastructure. Customer demand is a moving target and continuous hardware developments are necessary to supply higher data rates in an environmentally sustainable and cost effective way. This thesis reviews and advances the status of realizing wideband and high efficiency power amplifiers, which will facilitate improvements in network capacity and energy efficiency. Several demonstrator PAs are proposed, analyzed, designed, and characterized: First, resistive loading at higher harmonics in wideband power amplifier design suitable for envelope tracking (ET) is proposed. A 40 dBm decade bandwidth 0.4–4.1 GHz PA is designed, with 10–15 dB gain and 40–62% drain efficiency. Its versatility is demonstrated by digital pre-distortion (DPD) linearized measurements resulting in adjacent channel leakage ratios (ACLR) lower than −46 dBc for various downlink signals (WCDMA, LTE, WiMAX). Second, a theory for class-J microwave frequency dynamic load modulation (DLM) PAs is derived. This connects transistor technology and load network requirements to enable power-scalable and bandwidth conscious designs. A 38 dBm PA is designed at 2.08 GHz, maintaining efficiencies >45% over 8 dB of output power back-off (OPBO) dynamic range. From this pre-study a fully packaged 86-W peak power version at 2.14 GHz is designed. ACLR after DPD is −46 dBc at a drain efficiency of 34%. For DLM PAs there is a need for varactors with large effective tuning range and high breakdown voltage. For this purpose, SiC Schottky diode varactors are developed with an effective tuning range of 6:1 and supporting a 3:1 tuning ratio at 36 V of RF swing. Nonlinear characterization to enable Q-factor extraction in the presence of distortion is proposed and demonstrated by multi-harmonic active source- and load-pull, offering insights to tunable network design. Third, a method to evaluate and optimize dual-RF input PAs, while catering to higher harmonic conditions and transistor parasitics, is proposed. The method is validated by a PA design having a peak power of 44 +/- 0.9 dBm and 6 dB OPBO PAE exceeding 45% over a 1–3 GHz bandwidth. The results in this thesis contribute with a novel device and analysis of high efficiency and wideband PAs, aiding in the design of key components for future energy efficient and high capacity wireless systems

Technologies for the integration of Through Silicon Vias in MEMS packages

Ein vertikales Stapeln von Si-Chips stellt eine neue Möglichkeit zur Erhöhung der Bauelemente-Integrationsdichte in Gehäusen dar. Chips werden dafür aufeinander platziert, fixiert und untereinander durch vertiakle Durchführungen (Through Silion Vias) verbunden. In dieser Arbeit wird ein neuer Ansatz zur Integration von Through Silicon Vias in 3D MEMS - Aufbauten diskutiert

Pattern recognition in the nucleation kinetics of non-equilibrium self-assembly

Inspired by biology’s most sophisticated computer, the brain, neural networks constitute a profound reformulation of computational principles. Analogous high-dimensional, highly interconnected computational architectures also arise within information-processing molecular systems inside living cells, such as signal transduction cascades and genetic regulatory networks. Might collective modes analogous to neural computation be found more broadly in other physical and chemical processes, even those that ostensibly play non-information-processing roles? Here we examine nucleation during self-assembly of multicomponent structures, showing that high-dimensional patterns of concentrations can be discriminated and classified in a manner similar to neural network computation. Specifically, we design a set of 917 DNA tiles that can self-assemble in three alternative ways such that competitive nucleation depends sensitively on the extent of colocalization of high-concentration tiles within the three structures. The system was trained in silico to classify a set of 18 grayscale 30 × 30 pixel images into three categories. Experimentally, fluorescence and atomic force microscopy measurements during and after a 150 hour anneal established that all trained images were correctly classified, whereas a test set of image variations probed the robustness of the results. Although slow compared to previous biochemical neural networks, our approach is compact, robust and scalable. Our findings suggest that ubiquitous physical phenomena, such as nucleation, may hold powerful information-processing capabilities when they occur within high-dimensional multicomponent systems

Hydrogel-based logic circuits for planar microfluidics and lab-on-a-chip automation

The transport of vital nutrient supply in fluids as well as the exchange of specific chemical signals from cell to cell has been optimized over billion years of natural evolution. This model from nature is a driving factor in the field of microfluidics, which investigates the manipulation of the smallest amounts of fluid with the aim of applying these effects in fluidic microsystems for technical solutions. Currently, microfluidic systems are receiving attention, especially in diagnostics, \textit{e.g.} as SARS-CoV-2 antigen tests, or in the field of high-throughput analysis, \textit{e.g.} for cancer research. Either simple-to-use or large-scale integrated microfluidic systems that perform biological and chemical laboratory investigations on a so called Lab-on-a-Chip (LoC) provide fast analysis, high functionality, outstanding reproducibility at low cost per sample, and small demand of reagents due to system miniaturization. Despite the great progress of different LoC technology platforms in the last 30 years, there is still a lack of standardized microfluidic components, as well as a high-performance, fully integrated on-chip automation. Quite promising for the microfluidic system design is the similarity of the Kirchhoff's laws from electronics to predict pressure and flow rate in microchannel structures. One specific LoC platform technology approach controls fluids by active polymers which respond to specific physical and chemical signals in the fluid. Analogue to (micro-)electronics, these active polymer materials can be realized by various photolithographic and micro patterning methods to generate functional elements at high scalability. The so called chemofluidic circuits have a high-functional potential and provide “real” on-chip automation, but are complex in system design. In this work, an advanced circuit concept for the planar microfluidic chip architecture, originating from the early era of the semiconductor-based resistor-transistor-logic (RTL) will be presented. Beginning with the state of the art of microfluidic technologies, materials, and methods of this work will be further described. Then the preferred fabrication technology is evaluated and various microfluidic components are discussed in function and design. The most important component to be characterized is the hydrogel-based chemical volume phase transition transistor (CVPT) which is the key to approach microfluidic logic gate operations. This circuit concept (CVPT-RTL) is robust and simple in design, feasible with common materials and manufacturing techniques. Finally, application scenarios for the CVPT-RTL concept are presented and further development recommendations are proposed.:1 The transistor: invention of the 20th century 2 Introduction to fluidic microsystems and the theoretical basics 2.1 Fluidic systems at the microscale 2.2 Overview of microfluidic chip fabrication 2.2.1 Common substrate materials for fluidic microsystems 2.2.2 Structuring polymer substrates for microfluidics 2.2.3 Polymer chip bonding technologies 2.3 Fundamentals and microfluidic transport processes 2.3.1 Fluid dynamics in miniaturized systems 2.3.2 Hagen-Poiseuille law: the fluidic resistance 2.3.3 Electronic and microfluidic circuit model analogy 2.3.4 Limits of the electro-fluidic analogy 2.4 Active components for microfluidic control 2.4.1 Fluid transport by integrated micropumps 2.4.2 Controlling fluids by on-chip microvalves 2.4.3 Hydrogel-based microvalve archetypes 2.5 LoC technologies: lost in translation? 2.6 Microfluidic platforms providing logic operations 2.6.1 Hybrids: MEMS-based logic concepts 2.6.2 Intrinsic logic operators for microfluidic circuits 2.7 Research objective: microfluidic hydrogel-based logic circuits 3 Stimuli-responsive polymers for microfluidics 3.1 Introduction to hydrogels 3.1.1 Application variety of hydrogels 3.1.2 Hydrogel microstructuring methods 3.2 Theory: stimuli-responsive hydrogels 3.3 PNIPAAm: a multi-responsive hydrogel 4 Design, production and characterization methods of hydrogel-based microfluidic systems 4.1 The semi-automated computer aided design approach for microfluidic systems 4.2 The applied design process 4.3 Fabrication of microfluidic chips 4.3.1 Photoresist master fabrication 4.3.2 Soft lithography for PDMS chip production 4.3.3 Assembling PDMS chips by plasma bonding 4.4 Integration of functional hydrogels in microfluidic chips 4.4.1 Preparation of a monomer solution for hydrogel synthesis 4.4.2 Integration methods 4.5 Effects on hydrogel photopolymerization and the role of integration method 4.5.1 Photopolymerization from monomer solutions: managing the diffusion of free radicals 4.5.2 Hydrogel adhesion and UV light intensity distribution in the polymerization chamber 4.5.3 Hydrogel shrinkage behavior of different adhesion types 4.6 Comparison of the integration methods 4.7 Characterization setups for hydrogel actuators and microfluidic measurements . 71 4.7.1 Optical characterization method to describe swelling behavior 4.7.2 Setup of a microfluidic test stand 4.8 Conclusion: design, production and characterization methods 5 VLSI technology for hydrogel-based microfluidics 5.1 Overview of photolithography methods 5.2 Standard UV photolithography system for microfluidic structures 5.3 Self-made UV lithography system suitable for the mVLSI 5.3.1 Lithography setup for the DFR and SU-8 master exposure 5.3.2 Comparison of mask-based UV induced crosslinking for DFR and SU-8 5.4 Mask-based UV photopolymerization for mVLSI hydrogel patterning 5.4.1 Lithography setup for the photopolymerization of hydrogels 5.4.2 Hydrogel photopolymerization: experiments and results 5.4.3 Troubleshooting: photopolymerization of hydrogels 5.5 Conclusion: mVLSI technologies for hydrogel-based LoCs 6 Components for chemofluidic circuit design 6.1 Passive components in microfluidics 6.1.1 Microfluidic resistor 6.1.2 Planar-passive microfluidic signal mixer 6.1.3 Phase separation: laminar flow signal splitter 6.1.4 Hydrogel-based microfluidic one-directional valves 6.2 Hydrogel-based active components 6.2.1 Reversible hydrogel-based valves 6.2.2 Hydrogel-based variable resistors 6.2.3 CVPT: the microfluidic transistor 6.3 Conclusion: components for chemofluidic circuits 7 Hydrogel-based logic circuits in planar microfluidics 7.1 Development of a planar CVPT logic concept 7.1.1 Challenges of planar microfluidics 7.1.2 Preparatory work and conceptional basis 7.2 The microfluidic CVPT-RTL concept 7.3 The CVPT-RTL NAND gate 7.3.1 Circuit optimization stabilizing the NAND operating mode 7.3.2 Role of laminar flow for the CVPT-RTL concept 7.3.3 Hydrogel-based components for improved switching reliability 7.4 One design fits all: the NOR, AND and OR gate 7.5 Control measures for cascaded systems 7.6 Application scenarios for the CVPT-RTL concept 7.6.1 Use case: automated cell growth system 7.6.2 Use case: chemofluidic converter 7.7 Conclusion: Hydrogel-based logic circuits 8 Summary and outlook 8.1 Scientific achievements 8.2 Summarized recommendations from this work Supplementary information SI.1 Swelling degree of BIS-pNIPAAm gels SI.2 Simulated ray tracing of UV lithography setup by WinLens® SI.3 Determination of the resolution using the intercept theorem SI.4 Microfluidic master mold test structures SI.4.1 Polymer and glass mask comparison SI.4.2 Resolution Siemens star in DFR SI.4.3 Resolution Siemens star in SU-8 SI.4.4 Integration test array 300 μm for DFR and SU-8 SI.4.5 Integration test array 100 μm for SU-8 SI.4.6 Microfluidic structure for different technology parameters SI.5 Microfluidic test setups SI.6 Supplementary information: microfluidic components SI.6.1 Compensation methods for flow stabilization in microfluidic chips SI.6.2 Planar-passive microfluidic signal mixer SI.6.3 Laminar flow signal splitter SI.6.4 Variable fluidic resistors: flow rate characteristics SI.6.5 CVPT flow rate characteristics for high Rout Standard operation proceduresDer Transport von lebenswichtigen Nährstoffen in Flüssigkeiten sowie der Austausch spezifischer chemischer Signale von Zelle zu Zelle wurde in Milliarden Jahren natürlicher Evolution optimiert. Dieses Vorbild aus der Natur ist ein treibender Faktor im Fachgebiet der Mikrofluidik, welches die Manipulation kleinster Flüssigkeitsmengen erforscht um diese Effekte in fluidischen Mikrosystemen für technische Lösungen zu nutzen. Derzeit finden mikrofluidische Systeme vor allem in der Diagnostik, z.B. wie SARS-CoV-2-Antigentests, oder im Bereich der Hochdurchsatzanalyse, z.B. in der Krebsforschung, besondere Beachtung. Entweder einfach zu bedienende oder hochintegrierte mikrofluidische Systeme, die biologische und chemische Laboruntersuchungen auf einem sogenannten Lab-on-a-Chip (LoC) durchführen, bieten schnelle Analysen, hohe Funktionalität, hervorragende Reproduzierbarkeit bei niedrigen Kosten pro Probe und einen geringen Bedarf an Reagenzien durch die Miniaturisierung des Systems. Trotz des großen Fortschritts verschiedener LoC-Technologieplattformen in den letzten 30 Jahren mangelt es noch an standardisierten mikrofluidischen Komponenten sowie an einer leistungsstarken, vollintegrierten On-Chip-Automatisierung. Vielversprechend für das Design mikrofluidischer Systeme ist die Ähnlichkeit der Kirchhoff'schen Gesetze aus der Elektronik zur Vorhersage von Druck und Flussrate in Mikrokanalstrukturen. Ein spezifischer Ansatz der LoC-Plattformtechnologie steuert Flüssigkeiten durch aktive Polymere, die auf spezifische physikalische und chemische Signale in der Flüssigkeit reagieren. Analog zur (Mikro-)Elektronik können diese aktiven Polymermaterialien durch verschiedene fotolithografische und mikrostrukturelle Methoden realisiert werden, um funktionelle Elemente mit hoher Skalierbarkeit zu erzeugen.\\ Die sogenannten chemofluidischen Schaltungen haben ein hohes funktionales Potenzial und ermöglichen eine 'wirkliche' on-chip Automatisierung, sind jedoch komplex im Systemdesign. In dieser Arbeit wird ein fortgeschrittenes Schaltungskonzept für eine planare mikrofluidische Chiparchitektur vorgestellt, das aus der frühen Ära der halbleiterbasierten Resistor-Transistor-Logik (RTL) hervorgeht. Beginnend mit dem Stand der Technik der mikrofluidischen Technologien, werden Materialien und Methoden dieser Arbeit näher beschrieben. Daraufhin wird die bevorzugte Herstellungstechnologie bewertet und verschiedene mikrofluidische Komponenten werden in Funktion und Design diskutiert. Die wichtigste Komponente, die es zu charakterisieren gilt, ist der auf Hydrogel basierende chemische Volumen-Phasenübergangstransistor (CVPT), der den Schlüssel zur Realisierung mikrofluidische Logikgatteroperationen darstellt. Dieses Schaltungskonzept (CVPT-RTL) ist robust und einfach im Design und kann mit gängigen Materialien und Fertigungstechniken realisiert werden. Zuletzt werden Anwendungsszenarien für das CVPT-RTL-Konzept vorgestellt und Empfehlungen für die fortlaufende Entwicklung angestellt.:1 The transistor: invention of the 20th century 2 Introduction to fluidic microsystems and the theoretical basics 2.1 Fluidic systems at the microscale 2.2 Overview of microfluidic chip fabrication 2.2.1 Common substrate materials for fluidic microsystems 2.2.2 Structuring polymer substrates for microfluidics 2.2.3 Polymer chip bonding technologies 2.3 Fundamentals and microfluidic transport processes 2.3.1 Fluid dynamics in miniaturized systems 2.3.2 Hagen-Poiseuille law: the fluidic resistance 2.3.3 Electronic and microfluidic circuit model analogy 2.3.4 Limits of the electro-fluidic analogy 2.4 Active components for microfluidic control 2.4.1 Fluid transport by integrated micropumps 2.4.2 Controlling fluids by on-chip microvalves 2.4.3 Hydrogel-based microvalve archetypes 2.5 LoC technologies: lost in translation? 2.6 Microfluidic platforms providing logic operations 2.6.1 Hybrids: MEMS-based logic concepts 2.6.2 Intrinsic logic operators for microfluidic circuits 2.7 Research objective: microfluidic hydrogel-based logic circuits 3 Stimuli-responsive polymers for microfluidics 3.1 Introduction to hydrogels 3.1.1 Application variety of hydrogels 3.1.2 Hydrogel microstructuring methods 3.2 Theory: stimuli-responsive hydrogels 3.3 PNIPAAm: a multi-responsive hydrogel 4 Design, production and characterization methods of hydrogel-based microfluidic systems 4.1 The semi-automated computer aided design approach for microfluidic systems 4.2 The applied design process 4.3 Fabrication of microfluidic chips 4.3.1 Photoresist master fabrication 4.3.2 Soft lithography for PDMS chip production 4.3.3 Assembling PDMS chips by plasma bonding 4.4 Integration of functional hydrogels in microfluidic chips 4.4.1 Preparation of a monomer solution for hydrogel synthesis 4.4.2 Integration methods 4.5 Effects on hydrogel photopolymerization and the role of integration method 4.5.1 Photopolymerization from monomer solutions: managing the diffusion of free radicals 4.5.2 Hydrogel adhesion and UV light intensity distribution in the polymerization chamber 4.5.3 Hydrogel shrinkage behavior of different adhesion types 4.6 Comparison of the integration methods 4.7 Characterization setups for hydrogel actuators and microfluidic measurements . 71 4.7.1 Optical characterization method to describe swelling behavior 4.7.2 Setup of a microfluidic test stand 4.8 Conclusion: design, production and characterization methods 5 VLSI technology for hydrogel-based microfluidics 5.1 Overview of photolithography methods 5.2 Standard UV photolithography system for microfluidic structures 5.3 Self-made UV lithography system suitable for the mVLSI 5.3.1 Lithography setup for the DFR and SU-8 master exposure 5.3.2 Comparison of mask-based UV induced crosslinking for DFR and SU-8 5.4 Mask-based UV photopolymerization for mVLSI hydrogel patterning 5.4.1 Lithography setup for the photopolymerization of hydrogels 5.4.2 Hydrogel photopolymerization: experiments and results 5.4.3 Troubleshooting: photopolymerization of hydrogels 5.5 Conclusion: mVLSI technologies for hydrogel-based LoCs 6 Components for chemofluidic circuit design 6.1 Passive components in microfluidics 6.1.1 Microfluidic resistor 6.1.2 Planar-passive microfluidic signal mixer 6.1.3 Phase separation: laminar flow signal splitter 6.1.4 Hydrogel-based microfluidic one-directional valves 6.2 Hydrogel-based active components 6.2.1 Reversible hydrogel-based valves 6.2.2 Hydrogel-based variable resistors 6.2.3 CVPT: the microfluidic transistor 6.3 Conclusion: components for chemofluidic circuits 7 Hydrogel-based logic circuits in planar microfluidics 7.1 Development of a planar CVPT logic concept 7.1.1 Challenges of planar microfluidics 7.1.2 Preparatory work and conceptional basis 7.2 The microfluidic CVPT-RTL concept 7.3 The CVPT-RTL NAND gate 7.3.1 Circuit optimization stabilizing the NAND operating mode 7.3.2 Role of laminar flow for the CVPT-RTL concept 7.3.3 Hydrogel-based components for improved switching reliability 7.4 One design fits all: the NOR, AND and OR gate 7.5 Control measures for cascaded systems 7.6 Application scenarios for the CVPT-RTL concept 7.6.1 Use case: automated cell growth system 7.6.2 Use case: chemofluidic converter 7.7 Conclusion: Hydrogel-based logic circuits 8 Summary and outlook 8.1 Scientific achievements 8.2 Summarized recommendations from this work Supplementary information SI.1 Swelling degree of BIS-pNIPAAm gels SI.2 Simulated ray tracing of UV lithography setup by WinLens® SI.3 Determination of the resolution using the intercept theorem SI.4 Microfluidic master mold test structures SI.4.1 Polymer and glass mask comparison SI.4.2 Resolution Siemens star in DFR SI.4.3 Resolution Siemens star in SU-8 SI.4.4 Integration test array 300 μm for DFR and SU-8 SI.4.5 Integration test array 100 μm for SU-8 SI.4.6 Microfluidic structure for different technology parameters SI.5 Microfluidic test setups SI.6 Supplementary information: microfluidic components SI.6.1 Compensation methods for flow stabilization in microfluidic chips SI.6.2 Planar-passive microfluidic signal mixer SI.6.3 Laminar flow signal splitter SI.6.4 Variable fluidic resistors: flow rate characteristics SI.6.5 CVPT flow rate characteristics for high Rout Standard operation procedure