XEVE : an ESTEREL Verification Environment : (Version v1_3)

XEVE is a verification environment for ESTEREL programs modeled as Finite State Machines {FSMs) with a user-friendly graphical interface. The ESTEREL compiler translates a program into a system of boolean equations with latch that defines a FSM implicitly. XEVE works on these implicitly defined FSMs. It is based on the TiGeR library which provides efficient data structures and algorithms to manipulate FSMs symbolically using BDDs. It takes as input the set of boolean equations of a FSM described in the Blif format (Berkeley Logical Interchange Format). XEVE provides two main verification functions. The first function is the FSM state minimization using a notion of bisimulation equivalence that relates states indistinguishable when exploring the FSM graph from them. The minimization is made modulo a set of input/output signals declared as hidden. Minimized FSMs are generated explicitly in a textual format called Fc2 that can be loaded in the tool Atg for graphical exploration. The other verification function is the checking of the status of output signals: one can verify if an output is possibly emitted or not. This checking can be made modulo the fixing of input signals to some value (0 for absent or 1 for present). When an output is found possibly emitted or not, a minimal execution trace leading to a state emitting or not the signal is saved in the csimul format. The sequence can played within Xes the Esterel graphical simulator

Activity diagrams: a formal framework to model business processes and code generation

Activity Diagram is an important component of the set of diagrams used in UML. The OMG document on UML 2.0 proposes a Petri net based semantics for Activity Diagrams. While Petri net based approach is useful and interesting, it does not exploit the underlying inherent reactive behaviour of activity diagrams. In the first part of the paper, we shall capture activity diagrams in synchronous language framework to arrive at executional models which will be useful in model based design of software. This also enables validated code generation using code generation mechanism of synchronous language environments such as Esterel and its programming environments. Further, the framework leads to scalable verification methods. The traditional semantics proposed in OMG standard need enrichment when the activities are prone to failure and need compensating actions. Such extensions are expected to have applications in modelling complex business processes. In the second part of the paper, we propose an enrichment of the UML Activity Diagrams that include compensable actions. We shall use some of the foundations on Compensable Transactions and Communicating Sequential Processes due to Tony Hoare. This enriched formalism allows UML Activity Diagrams to model business processes that can fail and require compensating actions

An Iterative Method for the Design Process of Mode Handling Model

This paper focuses on formal verification and validation of a model dedicated to mode handling of flexible manufacturing systems. The model is specified using the synchronous formalism Safe State Machines. A structured framework for the design process is presented. The obtained model is characterized by a strong hierarchy and concurrency that is why within the design process an iterative approach for specification, verification and validation is propose in order to improve this process. The main properties being verified are presented and the approach is illustrated through an example of a manufacturing production cell

Верификация синхронно-автоматных программ

This article presents a synchronous model of the automaton program. A technique of verification of synchronous-automaton programs has been developed. Some properties of the model are checked automatically. There is an ability of verifying user-defined properties. This technique helps to discover errors often made during the design process.Предлагается синхронная модель автоматной программы. Разработана методика верификации синхронно-автоматных программ. Некоторые свойства проверяются автоматически. Есть возможность проверки пользовательских свойств. Применение этой методики позволит выявить большое число ошибок, допускаемых в процессе разработки

Modular Compilation of a Synchronous Language

Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing the reliability of systems, especially those which are safety or business critical. It is still difficult to develop automatic specification and verification tools due to limitations like state explosion, undecidability, etc... In this work, we design a new specification model based on a reactive synchronous approach. Then, we benefit from a formal framework well suited to perform compilation and formal validation of systems. In practice, we design and implement a special purpose language (LE) and its two semantics~: the ehavioral semantics helps us to define a program by the set of its behaviors and avoid ambiguousness in programs' interpretation; the execution equational semantics allows the modular compilation of programs into software and hardware targets (c code, vhdl code, fpga synthesis, observers). Our approach is pertinent considering the two main requirements of critical realistic applications~: the modular compilation allows us to deal with large systems, the model-based approach provides us with formal validation

Ackermann Encoding, Bisimulations, and OBDDs

We propose an alternative way to represent graphs via OBDDs based on the observation that a partition of the graph nodes allows sharing among the employed OBDDs. In the second part of the paper we present a method to compute at the same time the quotient w.r.t. the maximum bisimulation and the OBDD representation of a given graph. The proposed computation is based on an OBDD-rewriting of the notion of Ackermann encoding of hereditarily finite sets into natural numbers.Comment: To appear on 'Theory and Practice of Logic Programming