An Analytical Approach for Memristive Nanoarchitectures

As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nano-features and unique $I$-$V$ characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and hence provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.Comment: 12 pages, 10 figures, 4 table

Mesoscopic Models of Stochastic Transport

Transportphänomene treten in biologischen und künstlichen Systemen auf allen Längenskalen auf. In dieser Arbeit untersuchen wir sie für verschiedene Systeme aus einer mesoskopischen Perspektive, in der Fluktuationen physikalischer Größen um ihre Mittelwerte eine wichtige Rolle spielen. Im ersten Teil untersuchen wir die persistente Bewegung aktiver Brownscher Teilchen mit zusätzlichem Drehmoment, wie sie z.B. für Spermien oder Janus Teilchen auftritt. Wird ihre Bewegung auf einen Tunnel variierender Breite beschränkt, so setzt im thermischen Nichtgleichgewicht Transport ein; ungerichtete Fluktuationen des rauschhaften Antriebs werden gleichgerichtet. Hierdurch wird ein neuer Ratschentyp realisiert. Im zweiten Teil untersuchen wir den intrazellulären Cargotransport in den Axonen von Nervenzellen mithilfe molekularer Motoren. Sie werden als asymmetrischer Ausschlussprozess simuliert. Zusätzlich können die Cargos zwischen benachbarten Motoren ausgetauscht werden. Dadurch lassen sich charakteristische Eigenschaften des langsamen axonalen Transports mit einer einzigen Motorspezies reproduzieren. Bewerkstelligt wird dies durch die transiente Anbindung der Cargos an rückwärtslaufende Motorstaus. Im dritten Teil diskutieren wir resistive switching, die nicht volatile Widerstandsänderung eines Dielektrikums durch elektrische Impulse. Es wird für Anwendungen im Computerspeicher ausgenutzt, dem resistive RAM. Wir schlagen ein auf Sauerstoffvakanzen basierendes stochastisches Gitterhüpfmodell vor. Wir definieren binäre logische Zustände mit Hilfe der zugrunde liegenden Vakanzenverteilung und definieren Schreibe- und Leseoperationen durch Spannungsimpulse für ein solches Speicherelement. Überlegungen über die Unterscheidbarkeit dieser Operationen unter Fluktuationen zusammen mit der Deutlichkeit der unterschiedlichen Widerstandszustände selbst ermöglichen es uns, eine optimale Vakanzenzahl vorherzusagen.Transport phenomena occur in biological and artificial systems at all length scales. In this thesis, we investigate them for various systems from a mesoscopic perspective, in which fluctuations around their average properties play an important role. In the first part, we investigate the persistent diffusive motion of active Brownian particles with an additional torque. It can appear in many real life systems, for example in sperm cells or Janus particles. If their motion is confined to a tunnel of varying width, transport arises out of thermal equilibrium; unbiased fluctuations of the noisy drive are rectified. This way, we have realized a novel kind of ratchet. In the second part, we study intracellular cargo transport in the axons of nerve cells by molecular motors. They are modeled by an asymmetric exclusion process. In a new approach, we add a cargo exchange interaction between the motors. This way, the characteristics of slow axonal transport can be accounted for with a single motor species. It is explained by the transient attachment of cargos to reverse walking motors jams. In the third part, we discuss resistive switching, the non-volatile change of resistance in a dielectric due to electric pulses. It is exploited for applications in computer memory, the resistive random access memory (ReRAM). We propose a stochastic lattice hopping model based on the on oxygen vacancies. We define binary logical states by means of the underlying vacancy distributions, and establish a framework of writing and reading such a memory element with voltage pulses. Considerations about the discriminability of these operations under fluctuations together with the markedness of the resistive switching effect itself enable us to predict an optimal vacancy number

Nanoscale resistive switching memory devices: a review

In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I–V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed

New Approaches for Memristive Logic Computations

Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore\u27s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors. Memristors are non-volatile and nanoscale devices and can be used for building memory arrays with very high density (extending Moore\u27s law). Memristors can also be used to perform stateful logic operations where the same devices are used for logic and memory, enabling in-memory logic. In other words, memristor-based stateful logic enables a new computing paradigm of combining calculation and memory units (versus von Neumann architecture of separating calculation and memory units). This reduces the delays between processor and memory by eliminating redundant reloading of reusable values. In addition, memristors consume low power hence can decrease the large amounts of power dissipation in silicon chips hitting their size limit. The primary focus of this research is to develop the circuit implementations for logic computations based on memristors. These implementations significantly improve the performance and decrease the power of digital circuits. This dissertation demonstrates in-memory computing using novel memristive logic gates, which we call volistors (voltage-resistor gates). Volistors capitalize on rectifying memristors, i.e., a type of memristors with diode-like behavior, and use voltage at input and resistance at output. In addition, programmable diode gates, i.e., another type of logic gates implemented with rectifying memristors are proposed. In programmable diode gates, memristors are used only as switches (unlike volistor gates which utilize both memory and switching characteristics of the memristors). The programmable diode gates can be used with CMOS gates to increase the logic density. As an example, a circuit implementation for calculating logic functions in generalized ESOP (Exclusive-OR-Sum-of-Products) form and multilevel XOR network are described. As opposed to the stateful logic gates, a combination of both proposed logic styles decreases the power and improves the performance of digital circuits realizing two-level logic functions Sum-of-Products or Product-of-Sums. This dissertation also proposes a general 3-dimentional circuit architecture for in-memory computing. This circuit consists of a number of stacked crossbar arrays which all can simultaneously be used for logic computing. These arrays communicate through CMOS peripheral circuits