An algorithm to calculate the transport exponent in strip geometries

An algorithm for solving the random resistor problem by means of the transfer-matrix approach is presented. Preconditioning by spanning clusters extraction both reduces the size of the conductivity matrix and speed up the calculations.Comment: 17 pages, RevTeX2.1, HLRZ - 97/9

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis

Independent Orbiter Assessment (IOA): Analysis of the displays and controls subsystem

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA approach features a top-down analysis of the hardware to determine failure modes, criticality, and potential critical items. To preserve independence, this analysis was accomplished without reliance upon the results contained within the NASA FMEA/CIL documentation. This report documents the independent analysis results corresponding to the Orbiter Displays and Controls (D and C) subsystem hardware. The function of the D and C hardware is to provide the crew with the monitor, command, and control capabilities required for management of all normal and contingency mission and flight operations. The D and C hardware for which failure modes analysis was performed consists of the following: Acceleration Indicator (G-METER); Head Up Display (HUD); Display Driver Unit (DDU); Alpha/Mach Indicator (AMI); Horizontal Situation Indicator (HSI); Attitude Director Indicator (ADI); Propellant Quantity Indicator (PQI); Surface Position Indicator (SPI); Altitude/Vertical Velocity Indicator (AVVI); Caution and Warning Assembly (CWA); Annunciator Control Assembly (ACA); Event Timer (ET); Mission Timer (MT); Interior Lighting; and Exterior Lighting. Each hardware item was evaluated and analyzed for possible failure modes and effects. Criticality was assigned based upon the severity of the effect for each failure mode

Fourier-based schemes with modified Green operator for computing the electrical response of heterogeneous media with accurate local fields

A modified Green operator is proposed as an improvement of Fourier-based numerical schemes commonly used for computing the electrical or thermal response of heterogeneous media. Contrary to other methods, the number of iterations necessary to achieve convergence tends to a finite value when the contrast of properties between the phases becomes infinite. Furthermore, it is shown that the method produces much more accurate local fields inside highly-conducting and quasi-insulating phases, as well as in the vicinity of the phases interfaces. These good properties stem from the discretization of Green's function, which is consistent with the pixel grid while retaining the local nature of the operator that acts on the polarization field. Finally, a fast implementation of the "direct scheme" of Moulinec et al. (1994) that allows for parcimonious memory use is proposed.Comment: v2: `postprint' document (a few remaining typos in the published version herein corrected in red; results unchanged

Development of single-cell protectors for sealed silver-zinc cells

Three design approaches to cell-level protection were developed, fabricated, and tested. These systems are referred to as the single-cell protector (SCP), multiplexed-cell protector(MCP). To evaluate the systems 18-cell battery packs without cell level control were subjected to cycle life test. A total of five batteries were subjected to simulate synchronous orbit cycling at 40% depth of discharge at 22C. Batteries without cell-level protection failed between 345 and 255 cycles. Cell failure in the cell level protected batteries occurred between 412 and 540. It was determined that the cell-level monitoring and protection is necessary to attain the long cycle life of a AgZn battery. The best method of providing control and protection of the AgZn cells depends on the specific application and capability of the user

Validation by Measurements of a IC Modeling Approach for SiP Applications

The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi