Power supply noise analysis for 3D ICs using through-silicon-vias

3D design is being recognized widely as the next BIG thing in system integration. However, design and analysis tools for 3D are still in infancy stage. Power supply noise analysis is one of the critical aspects of a design. Hence, the area of noise analysis for 3D designs is a key area for future development. The following research presents a new parasitic RLC modeling technique for 3D chips containing TSVs as well as a novel optimization algorithm for power-ground network of a 3D chip with the aim of minimizing noise in the network. The following work also looks into an existing commercial IR drop analysis tool and presents a way to modify it with the aim of handling 3D designs containing TSVs.M.S.Committee Chair: Lim, Sung-Kyu; Committee Member: Lee, Hsien-Hsin Sean; Committee Member: Loh, Gabrie

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

Design and Characterization of a Standard Cell Library for the FREEPDK45 Process

The scope of this thesis can be summarized to two aspects. Firstly, to develop a design methodology to do layouts for a standard cell library to ensure no electrical and functional errors occur due to poor design of the cells when an IC is built out of them using CAD tools. The cell library has been built for the FREEPDK45 process following these rules and can be used for testing the emerging architectures in VLSI and research in academic institutions. Secondly, to establish procedures for characterizing a given cell library using Encounter library characterizer tool from Cadence in yielding correct results. The factors that determine the timing of the cells are studied and the setup to yield accurate results for the cell library developed has been presented. This library has been used in building a mixed signal integrated circuit, and the problems in completing the final physical verification (DRC and LVS) have been studied. The Cell library developed for the FREEPDK process has been characterized and abstracted. The library is tested for its structural correctness when input to CAD tools to construct an integrated circuit. The IC built has been verified to be DRC and LVS clean. The design rules established for building standard cell layouts can be used as a reference manual for designing any other library. The process of characterization is automated and made easy by the Encounter library characterizer tool. However, correctly setting up the tool is very important to yield correct results. The factors that determine this setup have been explored and documented which can also be used as a reference for characterizing any given cell library. The problems while doing LVS for an IC with multiple power domains using Calibre tool and the solution to eliminate them have been documented as well.School of Electrical & Computer Engineerin

Interconnect Planning for Physical Design of 3D Integrated Circuits

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary BibliographyDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliograph

Interconnect-driven floorplanning.

Sham Chiu Wing.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 107-113).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Progress on the Problem --- p.2Chapter 1.3 --- Our Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.5Chapter 2 --- Preliminaries --- p.6Chapter 2.1 --- Introduction --- p.6Chapter 2.1.1 --- The Role of Floorplanning --- p.6Chapter 2.1.2 --- Wirelength Estimation --- p.7Chapter 2.1.3 --- Different Types of Floorplan --- p.8Chapter 2.2 --- Representations of Floorplan --- p.10Chapter 2.2.1 --- Polish Expressions --- p.10Chapter 2.2.2 --- Sequence Pair --- p.11Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13Chapter 2.2.4 --- O-Tree --- p.14Chapter 2.2.5 --- B*-Tree --- p.16Chapter 2.2.6 --- Corner Block List --- p.18Chapter 2.2.7 --- Twin Binary Tree --- p.19Chapter 2.2.8 --- Comparisons between Different Representations --- p.20Chapter 2.3 --- Algorithms of Floorplan Design --- p.20Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22Chapter 2.3.4 --- Rectangular Dualization --- p.22Chapter 2.3.5 --- Simulated Annealing --- p.23Chapter 2.3.6 --- Genetic Algorithm --- p.23Chapter 2.4 --- Summary --- p.24Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25Chapter 3.1 --- Introduction --- p.25Chapter 3.2 --- Simulated Annealing Approach --- p.25Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27Chapter 3.3 --- Genetic Algorithm Approach --- p.28Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28Chapter 3.4 --- Force Directed Approach --- p.29Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29Chapter 3.5 --- Congestion Planning --- p.30Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31Chapter 3.6 --- Buffer Planning --- p.32Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35Chapter 3.7 --- Summary --- p.36Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37Chapter 4.1 --- Introduction --- p.37Chapter 4.2 --- Overview of the Floorplanner --- p.38Chapter 4.3 --- Congestion Model --- p.38Chapter 4.3.1 --- Construction of Grid Structure --- p.39Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40Chapter 4.3.3 --- Buffer Location Computation --- p.41Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43Chapter 4.4 --- Time Complexity --- p.44Chapter 4.5 --- Simulated Annealing --- p.45Chapter 4.6 --- Wirelength Estimation --- p.46Chapter 4.6.1 --- Center-to-center Estimation --- p.47Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48Chapter 4.7 --- Multi-pin Nets Handling --- p.49Chapter 4.8 --- Experimental Results --- p.50Chapter 4.9 --- Summary --- p.51Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53Chapter 5.1 --- Introduction --- p.53Chapter 5.2 --- Overview of the Floorplanner --- p.54Chapter 5.3 --- Congestion Model --- p.55Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57Chapter 5.3.2 --- Time Complexity --- p.61Chapter 5.4 --- Buffer Planning --- p.62Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69Chapter 5.5 --- Two-phases Simulated Annealing --- p.70Chapter 5.6 --- Wirelength Estimation --- p.72Chapter 5.7 --- Multi-pin Nets Handling --- p.73Chapter 5.8 --- Experimental Results --- p.73Chapter 5.9 --- Remarks --- p.76Chapter 5.10 --- Summary --- p.76Chapter 6 --- Global Router --- p.77Chapter 6.1 --- Introduction --- p.77Chapter 6.2 --- Overview of the Global Router --- p.77Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78Chapter 6.4 --- Multi-pin Nets Handling --- p.79Chapter 6.5 --- Routing Methodology --- p.79Chapter 6.6 --- Implementation --- p.80Chapter 6.7 --- Summary --- p.86Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87Chapter 7.1 --- Introduction --- p.87Chapter 7.2 --- Overview of the Method --- p.87Chapter 7.3 --- Searching Alternative Packings --- p.89Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89Chapter 7.3.2 --- Finding rearrangable module sets --- p.90Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94Chapter 7.4 --- Implementation --- p.97Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98Chapter 7.4.2 --- Cost Function --- p.101Chapter 7.4.3 --- Time Complexity --- p.101Chapter 7.5 --- Experimental Results --- p.101Chapter 7.6 --- Summary --- p.103Chapter 8 --- Conclusion --- p.105Bibliography --- p.10

SystemC-AMS thermal modeling for the co-simulation of functional and extra-functional properties

Temperature is a critical property of smart systems, due to its impact on reliability and to its inter-dependence with power consumption. Unfortunately, the current design flows evaluate thermal evolution ex-post, on offline power traces. This does not allow to consider temperature as a dimension in the design loop, and it misses all the complex inter-dependencies with design choices and power evolution. In this paper, by adopting the functional language SystemC-AMS, we propose a method to enable thermal/power/functional co-simulation. The system thermal model is built by using state-of-the-art circuit equivalent models, by exploiting the support for electrical linear networks intrinsic of SystemC-AMS. The experimental results will show that the choice of SystemC-AMS is a winning strategy for building a simultaneous simulation of multiple functional and extra-functional properties of a system. The generated code exposes an accuracy comparable to that of the reference thermal simulator HotSpot. Additionally, the initial overhead due to the general purpose nature of SystemC-AMS is compensated by surprisingly high performance of transient simulation, with speedups as high as two orders of magnitude

Timing-Driven Macro Placement

Placement is an important step in the process of finding physical layouts for electronic computer chips. The basic task during placement is to arrange the building blocks of the chip, the circuits, disjointly within a given chip area. Furthermore, such positions should result in short circuit interconnections which can be routed easily and which ensure all signals arrive in time. This dissertation mostly focuses on macros, the largest circuits on a chip. In order to optimize timing characteristics during macro placement, we propose a new optimistic timing model based on geometric distance constraints. This model can be computed and evaluated efficiently in order to predict timing traits accurately in practice. Packing rectangles disjointly remains strongly NP-hard under slack maximization in our timing model. Despite of this we develop an exact, linear time algorithm for special cases. The proposed timing model is incorporated into BonnMacro, the macro placement component of the BonnTools physical design optimization suite developed at the Research Institute for Discrete Mathematics. Using efficient formulations as mixed-integer programs we can legalize macros locally while optimizing timing. This results in the first timing-aware macro placement tool. In addition, we provide multiple enhancements for the partitioning-based standard circuit placement algorithm BonnPlace. We find a model of partitioning as minimum-cost flow problem that is provably as small as possible using which we can avoid running time intensive instances. Moreover we propose the new global placement flow Self-Stabilizing BonnPlace. This approach combines BonnPlace with a force-directed placement framework. It provides the flexibility to optimize the two involved objectives, routability and timing, directly during placement. The performance of our placement tools is confirmed on a large variety of academic benchmarks as well as real-world designs provided by our industrial partner IBM. We reduce running time of partitioning significantly and demonstrate that Self-Stabilizing BonnPlace finds easily routable placements for challenging designs – even when simultaneously optimizing timing objectives. BonnMacro and Self-Stabilizing BonnPlace can be combined to the first timing-driven mixed-size placement flow. This combination often finds placements with competitive timing traits and even outperforms solutions that have been determined manually by experienced designers

Physical parameter-aware Networks-on-Chip design

PhD ThesisNetworks-on-Chip (NoCs) have been proposed as a scalable, reliable and power-efficient communication fabric for chip multiprocessors (CMPs) and multiprocessor systems-on-chip (MPSoCs). NoCs determine both the performance and the reliability of such systems, with a significant power demand that is expected to increase due to developments in both technology and architecture. In terms of architecture, an important trend in many-core systems architecture is to increase the number of cores on a chip while reducing their individual complexity. This trend increases communication power relative to computation power. Moreover, technology-wise, power-hungry wires are dominating logic as power consumers as technology scales down. For these reasons, the design of future very large scale integration (VLSI) systems is moving from being computation-centric to communication-centric. On the other hand, chip’s physical parameters integrity, especially power and thermal integrity, is crucial for reliable VLSI systems. However, guaranteeing this integrity is becoming increasingly difficult with the higher scale of integration due to increased power density and operating frequencies that result in continuously increasing temperature and voltage drops in the chip. This is a challenge that may prevent further shrinking of devices. Thus, tackling the challenge of power and thermal integrity of future many-core systems at only one level of abstraction, the chip and package design for example, is no longer sufficient to ensure the integrity of physical parameters. New designtime and run-time strategies may need to work together at different levels of abstraction, such as package, application, network, to provide the required physical parameter integrity for these large systems. This necessitates strategies that work at the level of the on-chip network with its rising power budget. This thesis proposes models, techniques and architectures to improve power and thermal integrity of Network-on-Chip (NoC)-based many-core systems. The thesis is composed of two major parts: i) minimization and modelling of power supply variations to improve power integrity; and ii) dynamic thermal adaptation to improve thermal integrity. This thesis makes four major contributions. The first is a computational model of on-chip power supply variations in NoCs. The proposed model embeds a power delivery model, an NoC activity simulator and a power model. The model is verified with SPICE simulation and employed to analyse power supply variations in synthetic and real NoC workloads. Novel observations regarding power supply noise correlation with different traffic patterns and routing algorithms are found. The second is a new application mapping strategy aiming vii to minimize power supply noise in NoCs. This is achieved by defining a new metric, switching activity density, and employing a force-based objective function that results in minimizing switching density. Significant reductions in power supply noise (PSN) are achieved with a low energy penalty. This reduction in PSN also results in a better link timing accuracy. The third contribution is a new dynamic thermal-adaptive routing strategy to effectively diffuse heat from the NoC-based threedimensional (3D) CMPs, using a dynamic programming (DP)-based distributed control architecture. Moreover, a new approach for efficient extension of two-dimensional (2D) partially-adaptive routing algorithms to 3D is presented. This approach improves three-dimensional networkon- chip (3D NoC) routing adaptivity while ensuring deadlock-freeness. Finally, the proposed thermal-adaptive routing is implemented in field-programmable gate array (FPGA), and implementation challenges, for both thermal sensing and the dynamic control architecture are addressed. The proposed routing implementation is evaluated in terms of both functionality and performance. The methodologies and architectures proposed in this thesis open a new direction for improving the power and thermal integrity of future NoC-based 2D and 3D many-core architectures

Design methodology and productivity improvement in high speed VLSI circuits

2017 Spring.Includes bibliographical references.To view the abstract, please see the full text of the document