Wireless Testing of Integrated Circuits.

Integrated circuits (ICs) are usually tested during manufacture by means of automatic testing equipment (ATE) employing probe cards and needles that make repeated physical contact with the ICs under test. Such direct-contact probing is very costly and imposes limitations on the use of ATE. For example, the probe needles must be frequently cleaned or replaced, and some emerging technologies such as three-dimensional ICs cannot be probed at all. As an alternative to conventional probe-card testing, wireless testing has been proposed. It mitigates many of the foregoing problems by replacing probe needles and contact points with wireless communication circuits. However, wireless testing also raises new problems which are poorly understood such as: What is the most suitable wireless communication technique to employ, and how well does it work in practice? This dissertation addresses the design and implementation of circuits to support wireless testing of ICs. Various wireless testing methods are investigated and evaluated with respect to their practicality. The research focuses on near-field capacitive communication because of its efficiency over the very short ranges needed during IC manufacture. A new capacitive channel model including chip separation, cross-talk, and misalignment effects is proposed and validated using electro-magnetic simulation studies to provide the intuitions for efficient antenna and circuit design. We propose a compact clock and data recovery architecture to avoid a dedicated clock channel. An analytical model which predicts the DC-level fluctuation due to the capacitive channel is presented. Based on this model, feed-forward clock selection is designed to enhance performance. A method to select proper channel termination is discussed to maximize the channel efficiency for return-to-zero signaling. Two prototype ICs incorporating wireless testing systems were fabricated and tested with the proposed methods of testing digital circuits. Both successfully demonstrated gigahertz communication speeds with a bit-error rate less than 10^−11. A third prototype IC containing analog voltage measurement circuits was implemented to determine the feasibility of wirelessly testing analog circuits. The fabricated prototype achieved satisfactory voltage measurement with 1 mV resolution. Our work demonstrates the validity of the proposed models and the feasibility of near-field capacitive communication for wireless testing of ICs.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/93993/1/duelee_1.pd

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Power amplifier improvement techniques/circuits in 0.35 micron SiGe HBT technology for 5 ghz wireless LAN band

In this thesis, a 5 GHz radio frequency power amplifier for IEEE 802.11a WLAN applications is designed, the ideas of on-chip power combining and using transmission lines as an RF on-chip choke are tested and layouts are drawn. The power amplifier employs SiGe HBT’s in AMS 0.35 ´m BiCMOS process and it is designed to operate in Class A mode with a supply voltage of 3 Volts. Since the power amplifier is the final block and the final amplification stage of the transmitter chain in a wireless system, it must produce enough RF power to overcome the channel losses. At the same time, the power produced by the power amplifier should obey the power levels dictated by the operating standard. Therefore, in this work much consideration is given to design a power amplifier which provides enough output power for IEEE 802.11a WLAN standard. The power amplifier is designed to operate in Class A, and the bias points are chosen accordingly in order to preserve linearity. After the design of a single stage power amplifier, different versions of the circuit are designed and layouts are drawn. To decrease the dye area and the parasitic losses, the inductor which is used as the RF choke is replaced with capacitively loaded transmission lines. Moreover, in order to improve the linearity and obtain higher output power levels, two single stage power amplifiers are combined via on-chip Wilkinson power combiner made of lumped elements. Simulations are performed in ADS and Cadence environments in a parallel fashion

Multi-channel ultra-low-power receiver architecture for body area networks

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 85-91).In recently published integrated medical monitoring systems, a common thread is the high power consumption of the radio compared to the other system components. This observation is indicative of a natural place to attempt a reduction in system power. Narrowband receivers in-particular can enjoy significant power reduction by employing high-Q bulk acoustic resonators as channel select filters directly at RF, allowing down-stream analog processing to be simplified, resulting in better energy efficiency. But for communications in the ISM bands, it is important to employ multiple frequency channels to permit frequency-division-multiplexing and provide frequency diversity in the face of narrowband interferers. The high-Q nature of the resonators means that frequency tuning to other channels in the same band is nearly impossible; hence, a new architecture is required to address this challenge. A multi-channel ultra-low power OOK receiver for Body Area Networks (BANs) has been designed and tested. The receiver multiplexes three Film Bulk Acoustic Resonators (FBARs) to provide three channels of frequency discrimination, while at the same time offering competitive sensitivity and superior energy efficiency in this class of BAN receivers. The high-Q parallel resonance of each resonator determines the passband. The resonator's Q is on the order of 1000 and its center frequency is approximately 2.5 GHz, resulting in a -3 dB bandwidth of roughly 2.5 MHz with a very steep rolloff. Channels are selected by enabling the corresponding LNA and mixer pathway with switches, but a key benefit of this architecture is that the switches are not in series with the resonator and do not de-Q the resonance. The measured 1E-3 sensitivity is -64 dBm at 1 Mbps for an energy efficiency of 180 pJ/bit. The resonators are packaged beside the CMOS using wirebonds for the prototype.by Phillip Michel Nadeau.S.M

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies

Silicon Germanium BiCMOS Integrated Circuits for Scalable Cryogenic Sensing Applications

This dissertation is focused on an investigation of BiCMOS cryogenic low noise amplifiers (LNAs) based on Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for simultaneous low noise and low power design and also taking advantage of CMOS circuitry for adding flexibility to the LNA design. Cryogenic LNAs\u27 scalability challenges are discussed and addressed in the dissertation. To achieve that, first, HBTs of three state-of-the-art technologies are characterized and modeled at cryogenic temperature. It is shown that SiGe HBT provides a promising compromise of noise temperature, power consumption, and bandwidth. Moreover, a scalable on-chip approach is proposed and verified for biasing of SiGe HBTs based LNAs. Finally, the first cryogenic re-configurable LNA is designed, implemented, and measured

Lab-on-PCB Devices

Lab-on-PCB devices can be considered an emerging technology. In fact, most of the contributions have been published during the last 5 years. It is mainly focussed on both biomedical and electronic applications. The book includes an interesting guide for using the different layers of the Printed Circuit Boards for developing new devices; guidelines for fabricating PCB-based electrochemical biosensors, and an overview of fluid manipulation devices fabricated using Printed Circuit Boards. In addition, current PCB-based devices are reported, and studies for several aspects of research and development of lab-on-PCB devices are described

Development of an autonomous lab-on-a-chip system with ion separation and conductivity detection for river water quality monitoring

This thesis discusses the development of a lab on a chip (LOC) ion separation for river water quality monitoring using a capacitively coupled conductivity detector (C⁴D) with a novel baseline suppression technique.Our first interest was to be able to integrate such a detector in a LOC. Different designs (On-capillary design and on-chip design) have been evaluated for their feasibility and their performances. The most suitable design integrated the electrode close to the channel for an enhanced coupling while having the measurement electronics as close as possible to reduce noise. The final chip design used copper tracks from a printed circuit board (PCB) as electrodes, covered by a thin Polydimethylsiloxane (PDMS) layer to act as electrical insulation. The layer containing the channel was made using casting and bonded to the PCB using oxygen plasma. Flow experiments have been conduced to test this design as a detection cell for capacitively coupled contactless conductivity detection (C⁴D).The baseline signal from the system was reduced using a novel baseline suppression technique. Decrease in the background signal increased the dynamic range of the concentration to be measured before saturation occurs. The sensitivity of the detection system was also improved when using the baseline suppression technique. Use of high excitation voltages has proven to increase the sensitivity leading to an estimated limit of detection of 0.0715 μM for NaCl (0.0041 mg/L).The project also required the production of an autonomous system capable of operating for an extensive period of time without human intervention. Designing such a system involved the investigation of faults which can occur in autonomous system for the in-situ monitoring of water quality. Identification of possible faults (Bubble, pump failure, etc.) and detection methods have been investigated. In-depth details are given on the software and hardware architecture constituting this autonomous system and its controlling software