Fast Power and Energy Efficiency Analysis of FPGA-based Wireless Base-band Processing

Nowadays, demands for high performance keep on increasing in the wireless communication domain. This leads to a consistent rise of the complexity and designing such systems has become a challenging task. In this context, energy efficiency is considered as a key topic, especially for embedded systems in which design space is often very constrained. In this paper, a fast and accurate power estimation approach for FPGA-based hardware systems is applied to a typical wireless communication system. It aims at providing power estimates of complete systems prior to their implementations. This is made possible by using a dedicated library of high-level models that are representative of hardware IPs. Based on high-level simulations, design space exploration is made a lot faster and easier. The definition of a scenario and the monitoring of IP's time-activities facilitate the comparison of several domain-specific systems. The proposed approach and its benefits are demonstrated through a typical use case in the wireless communication domain.Comment: Presented at HIP3ES, 201

Dynamic Power Evaluation of LTE Wireless Baseband Processing on FPGA

International audienceMobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for FPGA-based systems is presented. It aims at providing accurate and fast power estimations of an entire system prior to its implementation. It also aims at making design space exploration easier. We introduce an innovative scenario-level in order to facilitate the comparison of domain-specific systems. We show the effectiveness of our approach on several LTE baseband configurations which leads to a low absolute error, compared to classic estimations. It also exhibits a high speed-up factor which is determinant during design space exploration. I. INTRODUCTION Today, the data traffic that is generated on mobile networks continues to grow rapidly. According to [1], global mobile data increases of 69% in 2014 and it will have a compound annual growth rate of 57% from 2014 to 2019. To deal with these issues, mobile networks and user equipments tend to constantly adapt their processing capabilities. Among all possible solutions, a popular example is the LTE standard. The complexity of systems like LTE makes their design and development a challenging task, especially when they are implemented in embedded systems in which specific constraints have to be taken into account (power, size, performance , etc.). The number of parameters that can have an impact over power consumption makes the power estimation even more difficult. As the new technologies clearly enhance the performance in terms of throughput, QoS, it also implies a higher power consumption and more heat dissipation. One of the most popular families of digital circuits in embedded systems are the Field Programmable Gate Arrays (FPGA). These devices represent an attractive technology and make it possible to implement complex systems due to their high density of gates and heterogeneous resources. As compare to ASIC that can achieve better performance [2], FPGAs offer more flexibility. FPGA-based systems can be made of IP (Intellectual Property) which are hardware cores that facilitate design reuse and speed up development time. Their power consumption is generally divided into static and dynamic power. Static power comes from leakage currents whereas dynamic power is generated by the transistors switching activity as soon as the circuit is active

System level modelling and design of hypergraph based wireless system area networks for multi-computer systems

This thesis deals with issues pertaining the wireless multicomputer interconnection networks namely topology and Medium Access Control (MAC). It argues that new channel assignment technique based on regular low-dimensional hypergraph networks, the dual radio wireless hypermesh, represents a promising alternative high-performance wireless interconnection network for the future multicomputers to shared communication medium networks and/or ordinary wireless mesh networks, which have been widely used in current wireless networks. The focus of this work is on improving the network throughput while maintaining a relatively low latency of a wireless network system. By means of a Carrier Sense Multiple Access (CSMA) based design of the MAC protocol and based on the desirable features of hypermesh network topology a relatively high performance network has been introduced. Compared to the CSMA shared communication channel model, which is currently the de facto MAC protocol for most of wireless networks, our design is shown to achieve a significant increase in network throughput with less average network latency for large number of communication nodes. SystemC model of the proposed wireless hypermesh, validated through mathematical models, are then introduced. The analysis has been incorporated in the proper SystemC design methodology which facilitates the integration of communication modelling into the design modelling at the early stages of the system development. Another important application of SystemC modelling techniques is to perform meaningful comparative studies of different protocols, or new implementations to determine which communication scenario performs better and the ability to modify models to test system sensitivity and tune performance. Effects of different design parameters (e.g., packet sizes, number of nodes) has been carried out throughout this work. The results shows that the proposed structure has out perform the existing shared medium network structure and it can support relatively high number of wireless connected computers than conventional networks

Wireless extension to the existing SystemC design methodology

This research uses a SystemC design methodology to model and design complex wireless communication systems, because in the recent years, the complexity of wireless communication systems has increased and the modelling and design of such systems has become inefficient and challenging. The most important aspect of modelling wireless communication systems is that system design choices may affect the communication behaviour and also communication design choices may impact on the system design. Whilst, the SystemC modelling language shows great promise in the modelling of complex hardware/software systems, it still lacks a standard framework that supports modelling of wireless communication systems (particularly the use of wireless communication channels). SystemC lacks elements and components that can be used to express and simulate wireless systems. It does not support noise links natively. To fill this gap, this research proposes to extend the existing SystemC design methodology to include an efficient simulation of wireless systems. It proposes to achieve this by employing a system-level model of a noisy wireless communication channel, along with a small repertoire of standard components (which of course can be replaced on a per application basis). Finally, to validate our developed methodology, a flocking behaviour system is selected as a demonstration (case study). This is a very complex system modelled based on the developed methodology and partitioned along different parameters. By applying our developed methodology to model this system as a case study, we can prove that incorporating and fixing the wireless channel, wireless protocol, noise or all of these elements early in the design methodology is very advantageous. The modelled system is introduced to simulate the behaviour of the particles (mobile units) that form a mobile ad-hoc communication network. Wireless communication between particles is addressed with two scenarios: the first is created using a wireless channel model to link each pair of particles, which means the wireless communication between particles is addressed using a Point-to-Point (P2P) channel; the other scenario is created using a shared channel (broadcast link). Therefore, incorporating wireless features into existing SystemC design methodology, as done in this research, is a very important task, because by developing SystemC as a design tool to support wireless systems, hardware aspects, software parts and communication can be modelled, refined and validated simultaneously on the same platform, and the design space expanded into a two-dimensional design space comprising system and communication

Addressing the Smart Systems Design Challenge: The SMAC Platform

This article presents the concepts, the organization, and the preliminary application results of SMAC, a smart systems co-design platform. The SMAC platform, which has been developed as Integrated Project (IP) of the 7th ICT Call under the Objective 3.2 \u201cSmart components and Smart Systems integration\u201d addresses the challenges of the integration of heterogeneous and conflicting domains that emerge in the design of smart systems. SMAC includes methodologies and EDA tools enabling multi-disciplinary and multi-scale modelling and design, simulation of multidomain systems, subsystems and components at different levels of abstraction, system integration and exploration for optimization of functional and non-functional metrics. The article presents the preliminary results obtained by adopting the SMAC platform for the design of a limb tracking smart system

On mixed abstraction, languages and simulation approach to refinement with SystemC AMS

Executable specifications and simulations arecornerstone to system design flows. Complex mixed signalembedded systems can be specified with SystemC AMSwhich supports abstraction and extensible models of computation. The language contains semantics for moduleconnections and synchronization required in analog anddigital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses Cbased interaction between simulators. An RTL model ofdata encryption standard is demonstrated as an example.The methodology is flexible and can be applied in earlydesign decision trade off, architecture experimentation and particularly for model refinement and critical behavior analysis

Simulation multi-moteurs multi-niveaux pour la validation des spécifications système et optimisation de la consommation

This work aims at system-level modelling a defined transceiver for Bluetooth Low energy (BLE) system using SystemC-AMS. The goal is to analyze the relationship between the transceiver performance and the accurate energy consumption. This requires the transceiver model contains system-level simulation speed and the low-level design block power consumption and other RF specifications. The Meet-in-the-Middle approach and the Baseband Equivalent method are chosen to achieve the two requirements above. A global simulation of a complete BLE system is achieved by integrating the transceiver model into a SystemC-TLM described BLE system model which contains the higher-than-PHY levels. The simulation is based on a two BLE devices communication system and is run with different BLE use cases. The transceiver Bit-Error-Rate and the energy estimation are obtained at the end of the simulation. First, we modelled and validated each block of a BT transceiver. In front of the prohibitive simulation time, the RF blocks are rewritten by using the BBE methodology, and then refined in order to take into account the non-linearities, which are going to impact the couple consumption, BER. Each circuit (each model) is separately verified, and then a first BLE system simulation (point-to-point between a transmitter and a receiver) has been executed. Finally, the BER is finally estimated. This platform fulfills our expectations, the simulation time is suitable and the results have been validated with the circuit measurement offered by Riviera Waves Company. Finally, two versions of the same transceiver architecture are modelled, simulated and comparedCe travail vise la modélisation au niveau système, en langage SystemC-AMS, et la simulation d'un émetteur-récepteur au standard Bluetooth Low Energy (BLE). L'objectif est d'analyser la relation entre les performances, en termes de BER et la consommation d'énergie du transceiver. Le temps de simulation d’un tel système, à partir de cas d’étude (use case) réaliste, est un facteur clé pour le développement d’une telle plateforme. De plus, afin d’obtenir des résultats de simulation le plus précis possible, les modèles « haut niveau » doivent être raffinés à partir de modèles plus bas niveau où de mesure. L'approche dite Meet-in-the-Middle, associée à la méthode de modélisation équivalente en Bande Base (BBE, BaseBand Equivalent), a été choisie pour atteindre les deux conditions requises, à savoir temps de simulation « faible » et précision des résultats. Une simulation globale d'un système de BLE est obtenue en intégrant le modèle de l'émetteur-récepteur dans une plateforme existante développée en SystemC-TLM. La simulation est basée sur un système de communication de deux dispositifs BLE, en utilisant différents scénarios (différents cas d'utilisation de BLE). Dans un premier temps nous avons modélisé et validé chaque bloc d’un transceiver BT. Devant le temps de simulation prohibitif, les blocs RF sont réécrits en utilisant la méthodologie BB, puis raffinés afin de prendre en compte les non-linéarités qui vont impacter le couple consommation, BER. Chaque circuit (chaque modèle) est vérifié séparément, puis une première simulation système (point à point entre un émetteur et un récepteur) est effectué

A high-level model of an embedded controller for an RF transceiver

Mobiililaitteessa voi nykyään olla useita radiolaitteita, tyypillisesti yksi tuettua radioprotokollaa kohti. Kukin radio lisää kustannuksia ja vie laitteesta tilaa. Koska halpa hinta ja pieni koko ovat usein tärkeitä mobiililaitteen suunnittelukriteerejä, kaikki mahdollisuudet tarvittavien komponenttien vähentämiseksi ja niiden koon pienentämiseksi otetaan innolla vastaan. Radioiden digitaalisten kantataajuuskomponenttien toiminnot voidaan parhaimmillaan yhdistellä yhden, riittävän nopean, yleiskäyttöisen prosessorin tehtäväksi. Tämä on nykyisin mahdollista, koska nykyisin on saatavilla riittävän nopeita prosessoreja. Yleiskäyttöinen prosessori pystyy nopeutensa vuoksi käsittelemään useiden samanaikaisten radioyhteyksien kantataajuiset datat. Sen sijaan radiotaajuuksia käsittelevien komponenttien osalta yhdistelymahdollisuudet ovat vielä pitkälti selvittämättä. Nykyisillä teknologioilla kaikesta komponenttien rinnakkaisuudesta ei vielä päästä eroon. Yhdistellyt komponentit tarvitsevat edeltäjistään poikkeavan ohjauksen. Yhdistelystä huolimatta komponenttien tulee edelleen tarjota sama toiminnallisuus kuin edeltäjiensä, mutta niiden täytyy olla joustavampia, sillä yhdisteltyjen komponenttien käyttäjät ovat vaihtelevampia kuin edeltäjien. Pitkän tähtäimen päämääränä komponentit halutaan karsia lukumääräisesti vähäisiksi, mutta toiminnoiltaan täysin joustaviksi, siten, että satunnainen radiojärjestelmä tai -protokolla voisi käyttää niitä. Kognitiivinen radio ja softaradio (Software De_ned Radio, SDR) ovat joustavia radiojärjestelmiä, joihin radioihin liittyvä tutkimus tähtää. Tässä työssä rakensimme korkean tason simulaattorimallin futuristisen radiotaajuuksia käsittelevän lähetinvastaanottimen osasta, erityiseseti sen kontrolleriohjelmistosta. Ohjelmisto mallintaa perinteisen, aina yhtä radiojärjestelmää vastaavan yhden signaalipolun sijaan radiotaajuuskomponentteja kontrolloivan ohjelmiston toiminnallisuutta sellaiselle radiolaitteelle, jossa kaikki radion osat ovat samanaikaisesti kaikkien radioprotokollien käytettävissä. Ohjelmisto mallintaa kontrollia protokollatasolta radiotaajuuskomponenttien digitaaliseen rajapintaan saakka. Simulaattori rakentuu kahden annetun rajapinnan varaan. Nämä ovat Lyra-metodilla tehty radiolaitteen rajapinta sekä yleiskäyttöisen radiotaajuuslähetinvastaanottimen rajapinta. Simulaattori rakennettiin SystemC-kirjastoa käyttäen. Mallin perusteella näyttää siltä, että protokollasta riippumaton, yleiskäyttöinen multiradiolähetinvastaanotin voidaan todella rakentaa siten, että useat samanaikaisesti aktiivisena olevat radioprotokollat voivat käyttää yleiskäyttöistä radiotaajuuslähetinvastaanotinta samanaikaisesti. Rakennettua mallia voidaan käyttää tarkempien radiomallien suunnittelun pohjana.A mobile hand-held may contain nowadays many di_erent radio devices, typically one for each of the radio protocols it supports. Each of these makes an additional cost and takes space on the device. As small cost and device size are important design factors for a mobile hand-held, any chance for reducing the number and size of needed components is warmly welcomed. Digital basebands can be seen to be mergeable to one generic processor due to increase in current processor speeds. A generic baseband processor is able to handle baseband processing for multiple radio connections concurrently, but it is yet to be seen how much integration can be done to the RF parts. With currently available technologies, we cannot get rid of all of the parallelism. The merged components require control di_erent from their predecessors. Merged components should still contain the functionality of the preceding components, but be more exibly controllable, as the callers are more diverse than before. Ultimately we would want to end up to a very few, fully exible components, usable by any radio protocol or radio system. Cognitive Radio and Software De_ned Radio are the aims the radio related research now strives for. In this thesis, we present a high-level system model of part of a futuristic RF radio, including controller software for a futuristic RF radio transceiver. The system models controller software for RF transceiver, whose sub-parts are concurrently usable by any radio protocol, instead of dedicated RF parts for each radio protocol or radio system. In the model, the control functionality that connects protocol-level commands to RF parts was modelled. The model is based on two interfaces. These are the Lyra model of the radio device interface, and an interface for a generic RF transceiver module. The model was made with SystemC. As the result, our model shows that a generic multiradio RF transceiver can be made controllable by several concurrently running radio protocols. The constructed model may be further used as a model for more accurate model-based radio system designs