Microwave Inter-Connections and Switching by means of Carbon Nano-tubes

In this work, carbon nanotube (CNT) based interconnections and switches will be reviewed, discussing the possibility to use nanotubes as potential building blocks for signal routing in microwave networks. In particular, theoretical design of coplanar waveguide (CPW), micro‐strip single‐pole‐single‐throw (SPST) and single‐pole‐double‐throw (SPDT) devices has been performed to predict the electrical performances of CNT‐based RF switching configurations. Actually, by using the semiconductor‐conductor transition obtained by properly biasing the CNTs, an isolation better than 30 dB can be obtained between the ON and OFF states of the switch for very wide bandwidth applications. This happens owing to the shape deformation and consequent change in the band‐gap due to the external pressure caused by the electric field. State‐of‐art for other switching techniques based on CNTs and their use for RF nano‐interconnections is also discussed, together with current issues in measurement techniques

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below